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Analog Devices AD9736 Evaluation Board AD9736-DPG2-EBZ AD9736-DPG2-EBZ Data Sheet

Product codes
AD9736-DPG2-EBZ
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Page of 72
 
AD9734/AD9735/AD9736
 
Rev. A | Page 33 of 72 
ANALOG CONTROL (ANA_CNT) REGISTERS (REG. 14, REG. 15) 
ADDR  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0x0E  
ANA_CNT1  
MSEL<1>  
MSEL<0>  
– – – 
TRMBG<2> 
 
TRMBG<1> TRMBG<0> 
0x0F  
ANA_CNT2  
HDRM<7>   HDRM<6>  
HDRM<5> 
HDRM<4> 
HDRM<3> 
HDRM<2>  
HDRM<1>  
HDRM<0>  
Table 16. Analog Control Register Bit Descriptions 
Bit Name 
Read/Write 
Description 
MSEL<1:0>  
WRITE  
00, mirror roll off frequency control = bypass. 
01, mirror roll off frequency control = narrowest bandwidth. 
10, mirror roll off frequency control = medium bandwidth.  
11
, mirror roll off frequency control = widest bandwidth. 
NOTE: See the plot in the Analog Control Registers section. 
TRMBG<2:0>  
WRITE  
000
, band gap temperature characteristic trim.  
NOTE: See the plot in the Analog Control Registers section.  
HDRM<7:0>  
WRITE  
0xCA, output stack headroom control. 
HDRM<7:4> set reference offset from AVDD33 (VCAS centering). 
HDRM<3:0> set overdrive (current density) trim (temperature tracking). 
Note: Set to 0xCA for optimum performance. 
BUILT-IN SELF TEST CONTROL (BIST_CNT) REGISTERS (REG. 17, REG. 18, REG. 19, REG. 20, REG. 21) 
ADDR   Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0x11  
BIST_CNT  
SEL<1>  
SEL<0>  
SIG_READ  
– 
– 
LVDS_EN  
SYNC_EN  
CLEAR  
0x12  
BIST<7:0>  
BIST<7>  
BIST<6>  
BIST<5>  
BIST<4>  
BIST<3>  
BIST<2>  
BIST<1>  
BIST<0>  
0x13  
BIST<15:8>  
BIST<15>  
BIST<14>  
BIST<13>  
BIST<12>  
BIST<11> 
BIST<10>  
BIST<9>  
BIST<8>  
0x14  
BIST<23:16>   BIST<23>  
BIST<22>  
BIST<21>  
BIST<20>  
BIST<19> 
BIST<18>  
BIST<17>  
BIST<16>  
0x15  
BIST<31:24>   BIST<31>  
BIST<30>  
BIST<29>  
BIST<28>  
BIST<27> 
BIST<26>  
BIST<25>  
BIST<24>  
Table 17. BIST Control Register Bit Descriptions 
Bit Name 
Read/Write 
Description 
SEL<1:0>  
WRITE  
00, write result of the LVDS Phase 1 BIST to BIST<31:0>. 
01, write result of the LVDS Phase 2 BIST to BIST<31:0>. 
10, write result of the SYNC Phase 1 BIST to BIST<31:0>. 
11, write result of the SYNC Phase 2 BIST to BIST<31:0>. 
SIG_READ WRITE 
0, no action. 
1, enable BIST signature readback. 
LVDS_EN WRITE 
0, no action. 
1, enable LVDS BIST. 
SYNC_EN WRITE 
0, no action. 
1, enable SYNC BIST. 
CLEAR WRITE  0, no action. 
1, clear all BIST registers. 
BIST<31:0> READ 
Results 
of the built-in self test.