Analog Devices AD9640 Evaluation Board AD9640-105EBZ AD9640-105EBZ Data Sheet
Product codes
AD9640-105EBZ
14-Bit, 80/105/125/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9640
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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FEATURES
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS
SFDR = 85 dBc to 70 MHz @ 125 MSPS
Low power: 750 mW @ 125 MSPS
SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3V CMOS output supply or 1.8 V LVDS
SFDR = 85 dBc to 70 MHz @ 125 MSPS
Low power: 750 mW @ 125 MSPS
SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3V CMOS output supply or 1.8 V LVDS
output supply
Integer 1 to 8 input clock divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
Composite signal monitor
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
Diversity radio systems
Multimode digital receivers
GSM, EDGE, WCDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Smart antenna systems
General-purpose software radios
Broadband data applications
FUNCTIONAL BLOCK DIAGRAM
06547-
001
VIN+A
VIN–A
VREF
SENSE
VIN–B
VIN+B
D13A
D0A
CLK+
CLK–
DCOA
DCOB
D13B
D0B
AGND
SYNC
FD(0:3)B
ADC
ADC
SIGNAL MONITOR
DATA
AVDD DVDD
FD(0:3)A
DRGND
PROGRAMMING DATA
DRVDD
FD BITS/THRESHOLD
DETECT
REF
SELECT
DUTY CYCLE
STABILIZER
MULTICHIP
SYNC
FD BITS/THRESHOLD
DETECT
SIGNAL MONITOR
INTERFACE
DCO
GENERATION
DIVIDE
1 TO 8
SIGNAL
MONITOR
SPI
CM
O
S
O
UT
P
UT
BU
F
F
E
R
CM
O
S
O
U
T
P
UT
BUF
F
E
R
SHA
SHA
CSB
SCLK/
DFS
SDIO/
DCS
CML
RBIAS
SMI
SDO/
OEB
SMI
SCLK/
PDWN
PDWN
SMI
SDFS
Figure 1.
PRODUCT HIGHLIGHTS
1.
Integrated dual 14-bit, 80/105/125/150 MSPS ADC.
2.
Fast overrange detect and signal monitor with serial output.
3.
Signal monitor block with dedicated serial output mode.
4.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz.
performance for input frequencies up to 450 MHz.
5.
Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
6.
A standard serial port interface that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, and voltage reference mode.
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, and voltage reference mode.
7.
Pin compatibility with the
, and the
bits, or 10 bits.