Data Sheet (AD9640-105EBZ)Table of ContentsFEATURES1APPLICATIONS1FUNCTIONAL BLOCK DIAGRAM1PRODUCT HIGHLIGHTS1TABLE OF CONTENTS2REVISION HISTORY3GENERAL DESCRIPTION4SPECIFICATIONS5ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-1055ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ1506ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-1057ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 1508DIGITAL SPECIFICATIONS9SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ10510SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ15011TIMING SPECIFICATIONS12Timing Diagrams12ABSOLUTE MAXIMUM RATINGS14THERMAL CHARACTERISTICS14ESD CAUTION14PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS15EQUIVALENT CIRCUITS19TYPICAL PERFORMANCE CHARACTERISTICS20THEORY OF OPERATION25ADC ARCHITECTURE25ANALOG INPUT CONSIDERATIONS25Input Common Mode25Differential Input Configurations25Single-Ended Input Configuration26VOLTAGE REFERENCE27Internal Reference Connection27External Reference Operation27CLOCK INPUT CONSIDERATIONS28Clock Input Options28Input Clock Divider29Clock Duty Cycle29Jitter Considerations29POWER DISSIPATION AND STANDBY MODE30DIGITAL OUTPUTS31Digital Output Enable Function (OEB)31TIMING31Data Clock Output (DCO)31ADC OVERRANGE AND GAIN CONTROL32FAST DETECT OVERVIEW32ADC FAST MAGNITUDE32ADC OVERRANGE (OR)33GAIN SWITCHING33Coarse Upper Threshold (C_UT)33Fine Upper Threshold (F_UT)33Fine Lower Threshold (F_LT)33Increment Gain (IG) and Decrement Gain (DG)33SIGNAL MONITOR35PEAK DETECTOR MODE35RMS/MS MAGNITUDE MODE35THRESHOLD CROSSING MODE36ADDITIONAL CONTROL BITS36Signal Monitor Enable Bit36Complex Power Calculation Mode Enable Bit36DC CORRECTION36DC Correction Bandwidth37DC Correction Readback37DC Correction Freeze37DC Correction Enable Bits37SIGNAL MONITOR SPORT OUTPUT37SMI SCLK37SMI SDFS37SMI SDO37BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST38BUILT-IN SELF-TEST (BIST)38OUTPUT TEST MODES38CHANNEL/CHIP SYNCHRONIZATION39SERIAL PORT INTERFACE (SPI)40CONFIGURATION USING THE SPI40HARDWARE INTERFACE40CONFIGURATION WITHOUT THE SPI41SPI ACCESSIBLE FEATURES41MEMORY MAP42READING THE MEMORY MAP TABLE42Open Locations42Default Values42Logic Levels42Transfer Register Map42Channel-Specific Registers42EXTERNAL MEMORY MAP43MEMORY MAP REGISTER DESCRIPTION46Sync Control (Register 0x100)46Bit 7—Signal Monitor Sync Enable46Bits[6:3]—Reserved46Bit 2—Clock Divider Next Sync Only46Bit 1—Clock Divider Sync Enable46Bit 0—Master Sync Enable46Fast Detect Control (Register 0x104)46Bits[7:4]—Reserved46Bits[3:1]—Fast Detect Mode Select46Bit 0—Fast Detect Enable46Fine Upper Threshold (Register 0x106 and Register 0x107)46Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0]46Register 0x107, Bits[7:5]—Reserved46Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8]46Fine Lower Threshold (Register 0x108 and Register 0x109)46Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0]Register 0x109, Bits[7:5]—ReservedRegister 0x109, Bits[4:0]—Fine Lower Threshold[12:8]46Signal Monitor DC Correction Control (Register 0x10C)46Bit 7—ReservedBit 6—DC Correction Freeze46Bits[5:2]—DC Correction Bandwidth46Bit 1—DC Correction for Signal Path Enable47Bit 0—DC Correction for SM Enable47Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)47Register 0x10D, Bits[7:0]—Channel A DC Value[7:0]47Register 0x10E, Bits[7:0]—Channel A DC Value[13:8]47Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)47Register 0x10F Bits[7:0]—Channel B DC Value[7:0]47Register 0x110 Bits[7:0]—Channel B DC Value[13:8]47Signal Monitor SPORT Control (Register 0x111)47Bit 7—Reserved47Bit 6—RMS/MS Magnitude Output Enable47Bit 5—Peak Power Output Enable47Bit 4—Threshold Crossing Output Enable47Bits[3:2]—SPORT SMI SCLK Divide47Bit 1— SPORT SMI SCLK Sleep47Bit 0—Signal Monitor SPORT Output Enable47Signal Monitor Control (Register 0x112)47Bit 7—Complex Power Calculation Mode Enable47Bits[6:4]—Reserved47Bit 3—Signal Monitor RMS/MS Select47Bits[2:1]—Signal Monitor Mode47Bit 0—Signal Monitor Enable47Signal Monitor Period (Register 0x113 to Register 0x115)47Register 0x113, Bits[7:0]—Signal Monitor Period[7:0]47Register 0x114, Bits[7:0]—Signal Monitor Period[15:8]47Register 0x115, Bits[7:0]—Signal Monitor Period[23:16]47Signal Monitor Result Channel A (Register 0x116 to Register 0x118)48Register 0x116, Bits[7:0]—Signal Monitor Result Channel A[7:0]48Register 0x117, Bits[7:0]—Signal Monitor Result Channel A[15:8]48Register 0x118, Bits[7:4]—Reserved48Register 0x118, Bits[3:0]—Signal Monitor Result Channel A[19:16]48Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)48Register 0x119, Bits[7:0]— Signal Monitor Result Channel B[7:0]48Register 0x11A, Bits[7:0]—Signal Monitor Result Channel B[15:8]48Register 0x11B, Bits[7:4]—Reserved48Register 0x11B, Bits[3:0]—Signal Monitor Result Channel B[19:16]48APPLICATIONS INFORMATION49DESIGN GUIDELINES49Power and Ground Recommendations49LVDS Operation49Exposed Paddle Thermal Heat Slug Recommendations49CML49RBIAS49Reference Decoupling49SPI Port49OUTLINE DIMENSIONS50ORDERING GUIDE51Size: 1.2 MBPages: 52Language: EnglishOpen manual