Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

ARM DDI0198D

B-9

To read an entry from the 2-way main TLB, the entry must first be written using the 
above instructions. The entry can then be read using the following instructions:

MRC p15, 4/5, <Rd>, c15, c2, 0 ; read tag main TLB
MRC p15, 4/5, <Rd>, c15, c4, 0 ; read PA/PROT main TLB

The data RAM attached to the main MMU is 112 bits wide. The mapping into the data 
RAM for main TLB writes for the TAG is shown below and would appear on 
MMUxWD[111:0] as shown in Table B-7.

During writes, the data is replicated so that each way receives the same copy of the data. 
The exact way that is written and the exact index of the way is specified in the Test and 
Debug Address Register. 

Figure B-5 on page B-10 shows what happens during a write to the data RAM attached 
to the main MMU.

1

[111:90]

TAG[31:10]

[89:86]

Size of entry

[85:64]

PA[31:10]

[63:60]

Domain select [3:0]

[59:58]

AP[1:0]

[57]

Cachable bit

[56]

Bufferable bit

0

[55:34]

TAG[31:10]

[33:30]

Size of entry

[29:8]

PA[31:10]

[7:4]

Domain select [3:0]

[3:2]

AP[1:0]

[1]

Cachable bit

[0]

Bufferable bit