Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
CP15 Test and Debug Registers
B-10
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
Figure B-5 Write to the data RAM
Note
On the rising clock edge when MMUxCS=1, the data on MMUxWD is written into the
data RAM. The exact index is on MMUxADDR (as specified in the Test and Debug
Address Register). The lanes written are controlled by the MMUxWE[3:0] pins. The
mapping is as follows:
data RAM. The exact index is on MMUxADDR (as specified in the Test and Debug
Address Register). The lanes written are controlled by the MMUxWE[3:0] pins. The
mapping is as follows:
MMUxWE[0]: 0= read, 1= write MMUxWD[ 29: 0] into RAM
MMUxWE[1]: 0= read, 1= write MMUxWD[ 55:30] into RAM
MMUxWE[2]: 0= read, 1= write MMUxWD[ 85:57] into RAM
MMUxWE[3]: 0= read, 1= write MMUxWD[111:86] into RAM
MMUxWE[1]: 0= read, 1= write MMUxWD[ 55:30] into RAM
MMUxWE[2]: 0= read, 1= write MMUxWD[ 85:57] into RAM
MMUxWE[3]: 0= read, 1= write MMUxWD[111:86] into RAM
In the case of the main MMU, the output enable MMUxOE is driven at all times. The
MMUxRD data bus must be strongly driven at all times. The controller samples the data
from the MMUxRD data bus when a read is being performed.
MMUxRD data bus must be strongly driven at all times. The controller samples the data
from the MMUxRD data bus when a read is being performed.
Inserting or reading entries in the lockdown TLB
Use this procedure to access entries in the lockdown TLB:
1.
Use the following Debug and Test Address Register instruction to access a
lockdown TLB entry:
lockdown TLB entry:
MCR p15, 0, <Rd>, c15, c1, 0
The Rd register selects the lockdown TLB entry as shown in Figure B-6 on
page B-11.
page B-11.
CLK
MMUxCS
IDX
MMUxADDR
LOC
MMUxWE
WDATA
MMUxWD
RDATA
MMUxRD
MMUxOE