Manualsbrain.com
en
Deutsch
Español
Français
Italiano
Português
Русский
조선말, 한국어
日本語
中文
Manuals
Brands
Atmel
ARM-Based Evaluation Kit AT91SAM9N12-EK
Data Sheet
Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Download
Like
Full screen
Standard
Page
of
248
Go
List of Tables
viii
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
Table 2-23
TCM Region Register c9 ........................................................................................ 2-30
Table 2-24
TCM Size field encoding ......................................................................................... 2-30
Table 2-25
Programming the TLB Lockdown Register ............................................................. 2-32
Table 2-26
FCSE PID Register operations ............................................................................... 2-34
Table 2-27
Context ID register operations ................................................................................ 2-35
Table 3-1
MMU program-accessible CP15 registers ................................................................ 3-4
Table 3-2
First-level descriptor bits ........................................................................................... 3-9
Table 3-3
Interpreting first-level descriptor bits [1:0] ............................................................... 3-10
Table 3-4
Section descriptor bits ............................................................................................ 3-11
Table 3-5
Coarse page table descriptor bits ........................................................................... 3-12
Table 3-6
Fine page table descriptor bits ................................................................................ 3-13
Table 3-7
Second-level descriptor bits .................................................................................... 3-15
Table 3-8
Interpreting page table entry bits [1:0] .................................................................... 3-16
Table 3-9
Priority encoding of fault status ............................................................................... 3-22
Table 3-10
FAR values for multi-word transfers ....................................................................... 3-23
Table 3-11
Domain access control register, access control bits ............................................... 3-24
Table 3-12
Interpreting access permission (AP) bits ................................................................ 3-24
Table 4-1
CP15 c1 I and M bit settings for the ICache ............................................................. 4-5
Table 4-2
Page table C bit settings for the ICache ................................................................... 4-5
Table 4-3
CP15 c1 C and M bit settings for the DCache .......................................................... 4-6
Table 4-4
Page table C and B bit settings for the DCache ....................................................... 4-6
Table 4-5
Instruction access priorities to the TCM and cache .................................................. 4-8
Table 4-6
Data access priorities to the TCM and cache ........................................................... 4-8
Table 4-7
Values of S and NSETS ......................................................................................... 4-10
Table 5-1
Relationship between DMDMAEN, DRDMACS, and DRIDLE ................................. 5-6
Table 6-1
Supported HBURST encodings ................................................................................ 6-4
Table 6-2
IHPROT[3:0] and DHPROT[3:0] attributes ............................................................... 6-5
Table 8-1
Handshake signal encoding ...................................................................................... 8-5
Table 8-2
CPBURST encoding ............................................................................................... 8-11
Table 11-1
Scan chain 15 format .............................................................................................. 11-2
Table 11-2
Scan chain 15 mapping to CP15 registers ............................................................. 11-4
Table A-1
AHB related signals .................................................................................................. A-3
Table A-2
Coprocessor interface signals .................................................................................. A-5
Table A-3
Debug signals ........................................................................................................... A-7
Table A-4
JTAG signals ............................................................................................................ A-9
Table A-5
Miscellaneous signals ............................................................................................. A-10
Table A-6
ETM interface signals ............................................................................................. A-12
Table A-7
TCM interface signals ............................................................................................. A-14
Table B-1
Debug Override Register .......................................................................................... B-3
Table B-2
Trace Control Register bit assignments .................................................................... B-5
Table B-3
MMU test operation instructions ............................................................................... B-5
Table B-4
Encoding of the main TLB entry-select bit fields ....................................................... B-6
Table B-5
Encoding of the TLB MVA tag bit fields .................................................................... B-7
Table B-6
Encoding of the TLB entry PA and AP bit fields ....................................................... B-8
Table B-7
Main TLB mapping to MMUxWD .............................................................................. B-9
Table B-8
Encoding of the lockdown TLB entry-select bit fields ............................................. B-11
Table B-9
Cache Debug Control Register bit assignments ..................................................... B-12
Prev
Next
1
…
6
7
8
9
10
…
248