Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos

Atmel

Los códigos de productos

AT91SAM9N12-EK

List of Tables

viii

Copyright © 2001-2003 ARM Limited. All rights reserved.

ARM DDI0198D

TCM Region Register c9 ........................................................................................ 2-30

TCM Size field encoding ......................................................................................... 2-30

Programming the TLB Lockdown Register ............................................................. 2-32

FCSE PID Register operations ............................................................................... 2-34

Context ID register operations ................................................................................ 2-35

MMU program-accessible CP15 registers ................................................................ 3-4

First-level descriptor bits ........................................................................................... 3-9

Interpreting first-level descriptor bits [1:0] ............................................................... 3-10

Section descriptor bits ............................................................................................ 3-11

Coarse page table descriptor bits ........................................................................... 3-12

Fine page table descriptor bits ................................................................................ 3-13

Second-level descriptor bits .................................................................................... 3-15

Interpreting page table entry bits [1:0] .................................................................... 3-16

Priority encoding of fault status ............................................................................... 3-22

FAR values for multi-word transfers ....................................................................... 3-23

Domain access control register, access control bits ............................................... 3-24

Interpreting access permission (AP) bits ................................................................ 3-24

CP15 c1 I and M bit settings for the ICache ............................................................. 4-5

Page table C bit settings for the ICache ................................................................... 4-5

CP15 c1 C and M bit settings for the DCache .......................................................... 4-6

Page table C and B bit settings for the DCache ....................................................... 4-6

Instruction access priorities to the TCM and cache .................................................. 4-8

Data access priorities to the TCM and cache ........................................................... 4-8

Values of S and NSETS ......................................................................................... 4-10

Relationship between DMDMAEN, DRDMACS, and DRIDLE ................................. 5-6

Supported HBURST encodings ................................................................................ 6-4

IHPROT[3:0] and DHPROT[3:0] attributes ............................................................... 6-5

Handshake signal encoding ...................................................................................... 8-5

CPBURST encoding ............................................................................................... 8-11

Scan chain 15 format .............................................................................................. 11-2

Scan chain 15 mapping to CP15 registers ............................................................. 11-4

AHB related signals .................................................................................................. A-3

Coprocessor interface signals .................................................................................. A-5

Debug signals ........................................................................................................... A-7

JTAG signals ............................................................................................................ A-9

Miscellaneous signals ............................................................................................. A-10

ETM interface signals ............................................................................................. A-12

TCM interface signals ............................................................................................. A-14

Debug Override Register .......................................................................................... B-3

Trace Control Register bit assignments .................................................................... B-5

MMU test operation instructions ............................................................................... B-5

Encoding of the main TLB entry-select bit fields ....................................................... B-6

Encoding of the TLB MVA tag bit fields .................................................................... B-7

Encoding of the TLB entry PA and AP bit fields ....................................................... B-8

Main TLB mapping to MMUxWD .............................................................................. B-9

Encoding of the lockdown TLB entry-select bit fields ............................................. B-11

Cache Debug Control Register bit assignments ..................................................... B-12