Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

308



Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate 
the timestamp.

The following example describes how to output trace data in asynchronous trace mode.



Configure the TPIU for asynchronous trace mode (refer to 

)



Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register 
(Address: 0xE0000FB0)



Write 0x00010015 into the Trace Control Register:

̶

Enable ITM

̶

Enable Synchronization packets

̶

Enable SWO behavior

̶

Fix the ATB ID to 1



Write 0x1 into the Trace Enable Register:

̶

Enable the Stimulus port 0



Write 0x1 into the Trace Privilege Register:

̶

Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the 
corresponding stimulus port being accessible in user mode.)



Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)

The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM).

The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.

The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The
TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port. As a consequence, asynchronous
trace mode is only available when the Serial Wire Debug mode is selected since TDO signal is used in JTAG
debug mode.

Two encoding formats are available for the single pin output:



 Manchester encoded stream. This is the reset value.



 NRZ_based UART byte structure

This example only concerns the asynchronous trace mode.



Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of 
trace and debug blocks.



Write 0x2 into the Selected Pin Protocol Register

̶

Select the Serial Wire Output – NRZ



Write 0x100 into the Formatter and Flush Control Register



Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the 
asynchronous output (this can be done automatically by the debugging tool).

IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.

IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAGSEL is high during power-up,
and must be kept in this state during the whole boundary scan operation. The SAMPLE, EXTEST and BYPASS