Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
306
Figure 13-4.
Debug Architecture
13.6.5 Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin
JTAG connector defined by ARM. For more details about voltage reference and reset state, please refer to the
“Signal Description” section of this datasheet.
JTAG connector defined by ARM. For more details about voltage reference and reset state, please refer to the
“Signal Description” section of this datasheet.
At start-up, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer
to the “Debug and Test” section of the product datasheet.
to the “Debug and Test” section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port
is not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO
mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad
for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode.
is not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO
mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad
for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAGSEL and PA7 pins are used to select the JTAG boundary scan when JTAGSEL is at high level and PA7
at low level. It integrates a permanent pull-down resistor of about 15 k
at low level. It integrates a permanent pull-down resistor of about 15 k
Ω to GND, so that it can be left unconnected
for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it
must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and
enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace.
must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and
enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be
used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to the
“Debug and Test” section of the datasheet.
used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to the
“Debug and Test” section of the datasheet.
SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP
and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed.
and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed.
4 watchpoints
PC sampler
data address sampler
data sampler
interrupt trace
CPU statistics
DWT
6 breakpoints
FPB
software trace
32 channels
time stamping
ITM
SWD/JTAG
SWJ-DP
SWO trace
TPIU
Table 13-2.
SWJ-DP Pin List
Pin Name
JTAG Port
Serial Wire Debug Port
TMS/SWDIO
TMS
SWDIO
TCK/SWCLK
TCK
SWCLK
TDI
TDI
-
TDO/TRACESWO
TDO
TRACESWO (optional: trace)