Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
315
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_02-Jun-14
EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the
RSTC_MR.
RSTC_MR.
The software reset is entered if at least one of these bits is set by the software. All these commands can be
performed independently or simultaneously. The software reset lasts 3 slow clock cycles.
performed independently or simultaneously. The software reset lasts 3 slow clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the software reset is left, i.e., synchronously to SLCK.
Clock (MCK). They are released when the software reset is left, i.e., synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the
resulting falling edge on NRST does not lead to a user reset.
resulting falling edge on NRST does not lead to a user reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the
Status register (RSTC_SR). Other software resets are not reported in RSTTYP.
Status register (RSTC_SR). Other software resets are not reported in RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the
RSTC_SR. It is cleared as soon as the software reset is left. No other software reset can be performed while the
SRCMP bit is set, and writing any value in the RSTC_CR has no effect.
RSTC_SR. It is cleared as soon as the software reset is left. No other software reset can be performed while the
SRCMP bit is set, and writing any value in the RSTC_CR has no effect.
Figure 14-5.
Software Reset
14.4.4.5 Watchdog Reset
The watchdog reset is entered when a watchdog fault occurs. This state lasts three
slow clock cycles.
When in watchdog reset, assertion of the reset signals depends on the WDRPROC bit in the WDT_MR:
If WDRPROC = 0, the processor reset and the peripheral reset are asserted. The NRST line is also
asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST
does not result in a user reset state.
asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST
does not result in a user reset state.
If WDRPROC = 1, only the processor reset is asserted.
SLCK
periph_nreset
if PERRST=1
proc_nreset
if PROCRST=1
Write RSTC_CR
NRST
(nrst_out)
if EXTRST=1
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 2 cycles
Any
Freq.
RSTTYP
Any
XXX
0x3 = Software Reset
Resynch.
1 cycle
SRCMP in RSTC_SR