Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

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SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_02-Jun-14

The Reset Controller status register (RSTC_SR) provides several status fields:



RSTTYP field: This field gives the type of the last reset, as explained in previous sections. 



SRCMP bit: This field indicates that a software reset command is in progress and that no further software 
reset should be performed until the end of the current one. This bit is automatically cleared at the end of the 
current software reset. 



NRSTL bit: The NRSTL bit of RSTC_SR gives the level of the NRST pin sampled on each MCK rising edge. 



URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR. This transition is 
also detected on the MCK rising edge (see 

). If the user reset is disabled (URSTEN = 0) and if 

the interruption is enabled by the URSTIEN bit in the RSTC_MR, the URSTS bit triggers an interrupt. 
Reading the RSTC_SR resets the URSTS bit and clears the interrupt.

MCK

NRST

NRSTL

2 cycle 

resynchronization

2 cycle

resynchronization

URSTS

read 

RSTC_SR

Peripheral Access

rstc_irq

if (URSTEN = 0) and

(URSTIEN = 1)