Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

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SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

The Cortex M Cache Controller (CMCC) is a 4-Way set associative unified cache controller. It integrates a
controller, a tag directory, data memory, metadata memory and a configuration interface.

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Physically addressed and physically tagged

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L1 data cache set to 2 Kbytes

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L1 cache line size set to 16 Bytes

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L1 cache integrates 32 bus master interface

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Unified Direct mapped cache architecture

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Unified 4-Way set associative cache architecture

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Write through cache operations, read allocate

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Round Robin victim selection policy

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Event Monitoring, with one programmable 32-bit counter

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Configuration registers accessible through Cortex M Private Peripheral Bus

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Cache Interface includes cache maintenance operations registers