Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
428
23.3
Block Diagram
Figure 23-1.
Block Diagram
23.4
Functional Description
23.4.1 Cache Operation
On reset, the cache controller data entries are all invalidated and the cache is disabled. The cache is transparent
to processor operations. The cache controller is activated with its configuration registers. The configuration
interface is memory mapped in the private peripheral bus.
to processor operations. The cache controller is activated with its configuration registers. The configuration
interface is memory mapped in the private peripheral bus.
Use the following sequence to enable the cache controller.
1.
Verify that the cache controller is disabled, reading the value of the CSTS (cache status) field of the CMCC_SR
register.
register.
2.
Enable the cache controller, writing 1 to the CEN (cache enable) field of the CMCC_CTRL register.
23.4.2 Cache Maintenance
If the contents seen by the cache has changed, the user needs to invalidate the cache entries. It can be done line
by line or for all cache entries.
by line or for all cache entries.
23.4.2.1 Cache Invalidate by Line Operation
When an invalidate by line command is issued the cache controller resets the valid bit information of the decoded
cache line. As the line is no longer valid the replacement counter points to that line.
cache line. As the line is no longer valid the replacement counter points to that line.
Use the following sequence to invalidate one line of cache.
1.
Disable the cache controller, writing 0 to the CEN field of the CMCC_CTRL register.
2.
Check CSTS field of the CMCC_SR to verify that the cache is successfully disabled.
Cache
Controller
Controller
METADATA RAM
DATA RAM
TAG RAM
RAM
Interface
Interface
Cortex M Interface
Memory Interface
Registers
Interface
Interface
APB
Interface
Interface
Cortex M Memory Interface Bus
System Memory Bus