Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
471
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
26.5.2 Memory Peripherals
shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no
handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once
the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative
to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the
peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait
states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus.
By using the handshaking interface, the peripheral can signal to the DMAC that it is ready to transmit/receive data,
and then the DMAC can access the peripheral without the peripheral inserting wait states onto the bus.
the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative
to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the
peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait
states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus.
By using the handshaking interface, the peripheral can signal to the DMAC that it is ready to transmit/receive data,
and then the DMAC can access the peripheral without the peripheral inserting wait states onto the bus.
26.5.3 Handshaking Interface
Handshaking interfaces are used at the transaction level to control the flow of single or chunk transfers. The
operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow
controller.
operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow
controller.
The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer/accept data over
the AMBA bus. A non-memory peripheral can request a DMAC transfer through the DMAC using one of two
handshaking interfaces:
the AMBA bus. A non-memory peripheral can request a DMAC transfer through the DMAC using one of two
handshaking interfaces:
Hardware handshaking
Software handshaking
Software selects between the hardware or software handshaking interface on a per-channel basis. Software
handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished
using a dedicated handshaking interface.
handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished
using a dedicated handshaking interface.
26.5.3.1 Software Handshaking
When the slave peripheral requires the DMAC to perform a DMAC transaction, it communicates this request by
sending an interrupt to the CPU or interrupt controller.
sending an interrupt to the CPU or interrupt controller.
The interrupt service routine then uses the software registers to initiate and control a DMAC transaction. These
software registers are used to implement the software handshaking interface.
software registers are used to implement the software handshaking interface.
The SRC_H2SEL/DST_H2SEL
bit in the DMAC_CFGx channel configuration register must be set to zero to
enable software handshaking.
When the peripheral is not the flow controller, then the last transaction register DMAC_LAST is not used, and the
values in these registers are ignored.
values in these registers are ignored.
Chunk Transactions
Writing a 1 to the DMAC_CREQ[2x] register starts a source chunk transaction request, where x is the channel
number. Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk transfer request, where x is the
channel number.
number. Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk transfer request, where x is the
channel number.
Upon completion of the chunk transaction, the hardware clears the DMAC_CREQ[2x] or DMAC_CREQ[2x+1].
Single Transactions
Writing a 1 to the DMAC_SREQ[2x] register starts a source single transaction request, where x is the channel
number. Writing a 1 to the DMAC_SREQ[2x+1] register starts a destination single transfer request, where x is the
channel number.
number. Writing a 1 to the DMAC_SREQ[2x+1] register starts a destination single transfer request, where x is the
channel number.
Upon completion of the chunk transaction, the hardware clears the DMAC_SREQ[x] or DMAC_SREQ[2x+1].
T he software can poll the relevant channe l b i t in the DMAC_ CREQ[2x]/DMAC_CREQ[2x+1] and
DMAC_SREQ[x]/DMAC_SREQ[2x+1] registers. When both are 0, then either the requested chunk or single
transaction has completed.
DMAC_SREQ[x]/DMAC_SREQ[2x+1] registers. When both are 0, then either the requested chunk or single
transaction has completed.