Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

473

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

Notes:

1.

USR means that the register field is manually programmed by the user.

2.

CONT means that address are contiguous.

3.

Channel stalled is true if the relevant BTC interrupt is not masked.

4.

LLI means that the register field is updated with the content of the linked list item.

In this case, the address between successive buffers is selected to be a continuation from the end of the previous
buffer. Enabling the source or destination address to be contiguous between buffers is a function of
DMAC_CTRLAx.SRC_DSCR and DMAC_CTRLAx.DST_DSCR registers.

At the end of every buffer transfer, an end of buffer interrupt is asserted if:



the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number.

Note:

The Buffer Transfer Completed Interrupt is generated at the completion of the buffer transfer to the destination.

At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:



the channel end of the Chained Buffer Transfer Completed Interrupt is unmasked, DMAC_EBCIMR.CBTCx 
= ‘1’, when n is the channel number.

System Memory

SADDRx

= DSCRx(0) + 0x0

DADDRx

= DSCRx(0) + 0x4

CTRLAx

= DSCRx(0) + 0x8

CTRLBx

= DSCRx(0) + 0xC

DSCRx(1)

= DSCRx(0) + 0x10

SADDRx

= DSCRx(1) + 0x0

DADDRx

= DSCRx(1) + 0x4

CTRLBx

= DSCRx(1) + 0x8

CTRLBx

= DSCRx(1) + 0xC

DSCRx(2)

= DSCRx(1) + 0x10

DSCRx(0)

DSCRx(2)
(points to 0 if
LLI(1) is the last
transfer descriptor

DSCRx(1)

LLI(0)

LLI(1)

1) Single Buffer or Last 

buffer of a multiple buffer 

transfer

–

–

USR

0

USR

USR

USR

2) Multi Buffer transfer with 

contiguous DADDR

0

1

LLI

USR

LLI

CONT

LLI

3) Multi Buffer transfer with 

contiguous SADDR

1

0

LLI

USR

CONT

LLI

LLI

4) Multi Buffer transfer with 

LLI support

0

0

LLI

USR

LLI

LLI

LLI