Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

Product codes
ATSAM4E-XPRO
Page of 1506
533
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
28.8.1.4 Null Delay Setup and Hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously
in case of consecutive read cycles in the same memory (see 
Figure 28-6.
No Setup, No Hold on NRD and NCS Read Signals
28.8.1.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
28.8.2 Read Mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data
is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first.
The READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
of NRD and NCS controls the read operation.
28.8.2.1 Read is Controlled by NRD (READ_MODE = 1):
 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available
t
PACC
 after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE
must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The
SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD,
whatever the programmed waveform of NCS may be.
MCK
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
NRD_PULSE
NCS_RD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_CYCLE
A[23:0]
NCS
NRD
D[7:0]