Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

Product codes
ATSAM4E-XPRO
Page of 1506
665
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
one other node has received the frame correctly. If not, an Acknowledge Error has occurred and the 
transmitter will start in the next bit-time an Error Frame transmission.
Fault Confinement
To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC
(Receive Error Counter) and TEC (Transmit Error Counter). The two counters are incremented upon detected
errors and are decremented upon correct transmissions or receptions, respectively. Depending on the counter
values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the
controller can send Error Active flags. The controller changes to the Error Passive state if there is an accumulation
of errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a state transition to Bus
Off.
Figure 33-7.
Line Error Mode
An error active unit takes part in bus communication and sends an active error frame when the CAN controller
detects an error.
An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is
detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating
further transmission.
A bus off unit is not allowed to have any influence on the bus.
For fault confinement, two errors counters (TEC and REC) are implemented. These counters are accessible via
the CAN_ECR. The state of the CAN controller is automatically updated according to these counter values. If the
CAN controller enters Error Active state, then the ERRA bit is set in the CAN_SR. The corresponding interrupt is
pending while the interrupt is not masked in the CAN_IMR. If the CAN controller enters Error Passive Mode, then
the ERRP bit is set in the CAN_SR and an interrupt remains pending while the ERRP bit is set in the CAN_IMR. If
the CAN enters Bus Off Mode, then the BOFF bit is set in the CAN_SR. As for ERRP and ERRA, an interrupt is
pending while the BOFF bit is set in the CAN_IMR. 
When one of the error counters values exceeds 96, an increased error rate is indicated to the controller through
the WARN bit in CAN_SR, but the node remains error active. The corresponding interrupt is pending while the
interrupt is set in the CAN_IMR.
Refer to the Bosch CAN specification v2.0 for details on fault confinement.
Error Interrupt Handler
ERRA, WARN, ERRP and BOFF (CAN_SR) store the key transitions of the CAN bus status as defined in 
The transitions depend on the TEC and REC (CAN_ECR) values as described in 
These flags are latched to keep from triggering a spurious interrupt in case these bits are used as the source of an
interrupt. Thus, these flags may not reflect the current status of the CAN bus.
ERROR 
ACTIVE
ERROR 
PASSIVE
 BUS OFF
TEC > 255
Init
TEC > 127
or
REC > 127
TEC < 127
and
REC < 127
128 occurences of 11 consecutive recessive bits
or
CAN controller reset