Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
474
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
presents the DMAC transfer flow.
Figure 32-9. DMAC Transfer Flow for Source and Destination Linked List Address
Channel enabled by
software
LLI Fetch
Hardware reprograms
SADDRx, DADDRx, CTRLA/Bx, DSCRx
DMAC buffer transfer
Writeback of DMAC_CTRLAx
register in system memory
Is DMAC in
Row 1 of
DMAC State Machine Table?
Channel disabled by
hardware
Chained Buffer Transfer Completed
Interrupt generated here
Interrupt generated here
DMAC Chained Buffer Transfer
Completed Interrupt generated here
Completed Interrupt generated here
yes
no