Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
1058
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
minimum period of the LCDDOTCK signal depends on the configuration. This information can be found in
The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the LCDCON2
register:
register:
• Always Active (used with TFT LCD Modules)
• Active only when data is available (used with STN LCD Modules)
The LCDDEN signal indicates valid data in the LCD Interface.
After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to cause the line to be
displayed on the panel.
displayed on the panel.
The following timing parameters can be configured:
• Vertical to Horizontal Delay (VHDLY): The delay between the falling edge of LCDVSYNC and the generation of
LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register. The delay is equal to (VHDLY+1)
LCDDOTCK cycles.
LCDDOTCK cycles.
• Horizontal Pulse Width (HPW): The LCDHSYNC pulse width is configurable in HPW field of LCDTIM2 register.
The width is equal to (HPW + 1) LCDDOTCK cycles.
• Horizontal Back Porch (HBP): The delay between the LCDHSYNC falling edge and the first LCDDOTCK rising
edge with valid data at the LCD Interface is configurable in the HBP field of the LCDTIM2 register. The delay is
equal to (HBP+1) LCDDOTCK cycles.
equal to (HBP+1) LCDDOTCK cycles.
• Horizontal Front Porch (HFP): The delay between end of valid data and the generation of the next LCDHSYNC
is configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+VHDLY+2) LCDDOTCK
cycles.
cycles.
There is a limitation in the minimum values of VHDLY, HPW and HBP parameters imposed by the initial latency of
the datapath. The total delay in LCDC clock cycles must be higher than or equal to the latency column in
the datapath. The total delay in LCDC clock cycles must be higher than or equal to the latency column in
Table 45-14.
Minimum LCDDOTCK Period in LCDC Core Clock Cycles
Configuration
LCDDOTCK Period
DISTYPE
SCAN
IFWIDTH
TFT
1
STN Mono
Single
4
4
STN Mono
Single
8
8
STN Mono
Dual
8
8
STN Mono
Dual
16
16
STN Color
Single
4
2
STN Color
Single
8
2
STN Color
Dual
8
4
STN Color
Dual
16
6
f
LCDDOTCK
f
LCDC_clock
CLKVAL
1
+
--------------------------------
=