Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
1060
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Figure 45-5.
STN Panel Timing, CLKMOD 0
Figure 45-6.
TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1
LCDHSYNC
LCDVSYNC
LCDDEN
LCDDOTCK
LCDD
Frame Period
VHDLY+
HBP+1
HPW+1
HFP+VHDLY+2
HOZVAL+1
LCDDOTCK
LCDD
1 PCLK
1/2 PCLK 1/2 PCLK
Line Period
LCDVSYNC
LCDHSYNC
LCDDEN
VHDLY+1 HBP+1
HPW+1
HFP+VHDLY+2
HOZVAL+1
LCDDOTCK
LCDD
1 PCLK
1/2 PCLK 1/2 PCLK
Line Period
LCDVSYNC
LCDHSYNC
LCDDEN
(VPW+1) Lines
LCDVSYNC
LCDDOTCK
LCDD
LCDDEN
VHDLY+1
LCDHSYNC
Vertical Fron t Porch = VFP Lines
Vertical Back Porch = VBP Lines
Frame Period