Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

– Program the CSS field in the PMC_MCKR register.

– Wait for the MCKRDY bit to be set in the PMC_SR register.

• If a new value for CSS field corresponds to Main Clock or Slow Clock,

– Program the CSS field in the PMC_MCKR register.

– Wait for the MCKRDY bit to be set in the PMC_SR register.

– Program the PRES field in the PMC_MCKR register.

– Wait for the MCKRDY bit to be set in the PMC_SR register.

If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to
indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit
to be set again before using the Master and Processor Clocks.

Note:

IF PLLA clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLAR, the 
MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again, LOCK goes high and MCKRDY is set.
While PLLA is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, 
see 

Code Example: 

write_register(PMC_MCKR,0x00000001)

wait (MCKRDY=1)

write_register(PMC_MCKR,0x00000011)

wait (MCKRDY=1)

The Master Clock is main clock divided by 16.

The Processor Clock is the Master Clock.

5.

Selection of Programmable clocks

Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR.

Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers.
Depending on the system used, 2 programmable clocks can be enabled or disabled. The PMC_SCSR pro-
vides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are
disabled.

PMC_PCKx registers are used to configure programmable clocks.

The CSS and CSSMCK fields are used to select the programmable clock divider source. Five clock options are
available: main clock, slow clock, master clock, PLLACK, UPLLCK. By default, the clock source selected is
slow clock.

The PRES field is used to control the programmable clock prescaler. It is possible to choose between different
values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By
default, the PRES parameter is set to 1 which means that master clock is equal to slow clock.

Once the PMC_PCKx register has been programmed, The corresponding programmable clock must be
enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be
done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to
PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a
single write operation.