Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
346
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
z
Software Reset bit in the Control A register (CTRLA.SWRST)
z
Enable bit in the Control A register (CTRLA.ENABLE)
z
Receiver Enable bit in the Control B register (CTRLB.RXEN)
z
Transmitter Enable bit in the Control B register (CTRLB.TXEN)
CTRLB.RXEN and CTRLB.TXEN behave somewhat differently than described above. Refer to CTRLB register
description for details.
description for details.
Synchronization is denoted by the Write-Synchronized property in the register description.