Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
348
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
24.8
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to
the Write-Protected property in each individual register description. Refer to
for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Synchronized
property in each individual register description. Refer to
property in each individual register description. Refer to
Some registers are enable-protected, meaning they can only be written when the USART is disabled. Enable-protection
is denoted by the Enable-Protected property in each individual register description.
is denoted by the Enable-Protected property in each individual register description.
24.8.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x00000000
Property:
Enable-Protected, Write-Protected, Write-Synchronized
z
Bit 31 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit
31
30
29
28
27
26
25
24
DORD
CPOL
CMODE
FORM[3:0]
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RXPO[1:0]
TXPO
Access
R
R
R/W
R/W
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
IBON
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RUNSTDBY
MODE[2:0]
ENABLE
SWRST
Access
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0