Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet

1043

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

The large number of source clocks can make selection difficult. The relationship between the value in the 

 (PWM_CPRDx) and the 

 (PWM_CDTYx) can help the

user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty-Cycle
quantum cannot be lower than 1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM
accuracy. 

For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value from between 1 up to
14 in PWM_CDTYx. The resulting duty-cycle quantum cannot be lower than 1/15 of the PWM period.

It is possible to modulate the output waveform duty-cycle, period and dead-times. 

To prevent unexpected output waveform, the user must use the 

(PWM_CDTYUPDx), the 

 (PWM_CPRDUPDx) and the 

 (PWM_DTUPDx) to change waveform parameters while the channel is still enabled.



If the channel is an asynchronous channel (SYNCx = 0 in 

(PWM_SCM)), these registers hold the new period, duty-cycle and dead-times values until the end of the 
current PWM period and update the values for the next period.



If the channel is a synchronous channel and update method 0 is selected (SYNCx = 1 and UPDM = 0 in 
PWM_SCM register), these registers hold the new period, duty-cycle and dead-times values until the bit 
UPDULOCK is written at ‘1’ (in 

 (PWM_SCUC)) and the end 

of the current PWM period, then update the values for the next period.



If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx = 1 and UPDM = 1 or 
2 in PWM_SCM register):

̶

registers PWM_CPRDUPDx and PWM_DTUPDx hold the new period and dead-times values until the 
bit UPDULOCK is written at ‘1’ (in PWM_SCUC) and the end of the current PWM period, then update 
the values for the next period. 

̶

register PWM_CDTYUPDx holds the new duty-cycle value until the end of the update period of 
synchronous channels (when UPRCNT is equal to UPR in 

 (PWM_SCUP)) and the end of the current PWM period, then updates the value for the next 

period.

Note:

If the update registers PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx are written several times between 
two updates, only the last written value is taken into account.