Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK User Manuals

Table of Contents

• Description

  1
• 1. Features

  2
  • 1.1 Configuration Summary

    4
• 2. Block Diagram

  5
• 3. Signal Description

  7
• 4. Package and Pinout

  11
  • 4.1 100-ball TFBGA Package and Pinout

    11
    • 4.1.1 100-ball TFBGA Package Outline

      11
    • 4.1.2 100-ball TFBGA Pinout

      11
  • 4.2 144-ball LFBGA Package and Pinout

    12
    • 4.2.1 144-ball LFBGA Package Outline

      12
    • 4.2.2 144-ball LFBGA Pinout

      12
  • 4.3 100-lead LQFP Package and Pinout

    13
    • 4.3.1 100-lead LQFP Package Outline

      13
    • 4.3.2 100-lead LQFP Pinout

      13
  • 4.4 144-lead LQFP Package and Pinout

    14
    • 4.4.1 144-lead LQFP Package Outline

      14
    • 4.4.2 144-lead LQFP Pinout

      14
• 5. Power Considerations

  15
  • 5.1 Power Supplies

    15
  • 5.2 Voltage Regulator

    15
  • 5.3 Typical Powering Schematics

    15
  • 5.5 Low-power Modes

    16
    • 5.5.1 Backup Mode

      16
    • 5.5.2 Wait Mode

      17
    • 5.5.3 Sleep Mode

      18
    • 5.5.4 Low-power Mode Summary Table

      19
  • 5.6 Wake-up Sources

    20
  • 5.7 Fast Start-up

    21
• 6. Input/Output Lines

  22
  • 6.1 General Purpose I/O Lines

    22
  • 6.2 System I/O Lines

    23
• 7. Product Mapping

  24
• 8. Memories

  25
  • 8.1 Embedded Memories

    25
    • 8.1.1 Internal SRAM

      25
    • 8.1.2 Internal ROM

      25
    • 8.1.3 Embedded Flash

      25
      • 8.1.3.1 Flash Overview

        25
      • 8.1.3.2 Enhanced Embedded Flash Controller

        27
      • 8.1.3.3 Flash Speed

        27
      • 8.1.3.4 Lock Regions

        27
      • 8.1.3.5 Security Bit Feature

        27
      • 8.1.3.6 Calibration Bits

        28
      • 8.1.3.7 Unique Identifier

        28
      • 8.1.3.8 User Signature

        28
      • 8.1.3.9 Fast Flash Programming Interface

        28
      • 8.1.3.10 SAM-BA Boot

        28
      • 8.1.3.11 GPNVM Bits

        28
    • 8.1.4 Boot Strategies

      29
  • 8.2 External Memories

    30
  • 8.3 Cortex-M Cache Controller (CMCC)

    30
• 9. Real-time Event Management

  31
  • 9.1 Embedded Characteristics

    31
  • 9.2 Real-time Event Mapping List

    32
• 10. System Controller

  33
  • 10.1 System Controller and Peripherals Mapping

    34
  • 10.2 Power-on-Reset, Brownout and Supply Monitor

    35
    • 10.2.1 Power-on-Reset

      35
    • 10.2.2 Brownout Detector on VDDCORE

      35
    • 10.2.3 Supply Monitor on VDDIO

      35
  • 10.3 Reset Controller

    35
• 11. Peripherals

  37
  • 11.1 Peripheral Identifiers

    37
  • 11.2 Peripheral Signal Multiplexing on I/O Lines

    39
    • 11.2.1 PIO Controller A Multiplexing

      40
    • 11.2.2 PIO Controller B Multiplexing

      41
    • 11.2.3 PIO Controller C Multiplexing

      42
    • 11.2.4 PIO Controller D Multiplexing

      43
    • 11.2.5 PIO Controller E Multiplexing

      44
• 12. ARM Cortex-M4 Processor

  45
  • 12.1 Description

    45
    • 12.1.1 System Level Interface

      45
    • 12.1.2 Integrated Configurable Debug

      45
  • 12.2 Embedded Characteristics

    46
  • 12.3 Block Diagram

    46
  • 12.4 Cortex-M4 Models

    47
    • 12.4.1 Programmers Model

      47
      • 12.4.1.1 Processor Modes and Privilege Levels for Software Execution

        47
      • 12.4.1.2 Stacks

        47
      • 12.4.1.3 Core Registers

        48
      • 12.4.1.4 General-purpose Registers

        49
      • 12.4.1.5 Stack Pointer

        49
      • 12.4.1.6 Link Register

        49
      • 12.4.1.7 Program Counter

        49
      • 12.4.1.8 Program Status Register

        50
      • 12.4.1.9 Application Program Status Register

        51
      • 12.4.1.10 Interrupt Program Status Register

        52
      • 12.4.1.11 Execution Program Status Register

        53
      • 12.4.1.12 Exception Mask Registers

        54
      • 12.4.1.13 Priority Mask Register

        55
      • 12.4.1.14 Fault Mask Register

        56
      • 12.4.1.15 Base Priority Mask Register

        57
      • 12.4.1.16 Control Register

        58
      • 12.4.1.17 Exceptions and Interrupts

        60
      • 12.4.1.18 Data Types

        60
      • 12.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS)

        60
    • 12.4.2 Memory Model

      61
      • 12.4.2.1 Memory Regions, Types and Attributes

        61
      • 12.4.2.2 Memory System Ordering of Memory Accesses

        62
      • 12.4.2.3 Behavior of Memory Accesses

        63
      • 12.4.2.4 Software Ordering of Memory Accesses

        64
      • 12.4.2.5 Bit-banding

        64
      • 12.4.2.6 Memory Endianness

        66
      • 12.4.2.7 Synchronization Primitives

        67
      • 12.4.2.8 Programming Hints for the Synchronization Primitives

        68
    • 12.4.3 Exception Model

      68
      • 12.4.3.1 Exception States

        68
      • 12.4.3.2 Exception Types

        69
      • 12.4.3.3 Exception Handlers

        71
      • 12.4.3.4 Vector Table

        71
      • 12.4.3.5 Exception Priorities

        72
      • 12.4.3.6 Interrupt Priority Grouping

        72
      • 12.4.3.7 Exception Entry and Return

        72
      • 12.4.3.8 Fault Handling

        76
  • 12.5 Power Management

    78
    • 12.5.1 Entering Sleep Mode

      78
      • 12.5.1.1 Wait for Interrupt

        78
      • 12.5.1.2 Wait for Event

        78
      • 12.5.1.3 Sleep-on-exit

        78
    • 12.5.2 Wakeup from Sleep Mode

      78
      • 12.5.2.1 Wakeup from WFI or Sleep-on-exit

        78
      • 12.5.2.2 Wakeup from WFE

        78
      • 12.5.2.3 External Event Input

        79
    • 12.5.3 Power Management Programming Hints

      79
  • 12.6 Cortex-M4 Instruction Set

    80
    • 12.6.1 Instruction Set Summary

      80
    • 12.6.2 CMSIS Functions

      86
    • 12.6.3 Instruction Descriptions

      87
      • 12.6.3.1 Operands

        87
      • 12.6.3.2 Restrictions when Using PC or SP

        87
      • 12.6.3.3 Flexible Second Operand

        87
      • 12.6.3.4 Shift Operations

        88
      • 12.6.3.5 Address Alignment

        90
      • 12.6.3.6 PC-relative Expressions

        90
      • 12.6.3.7 Conditional Execution

        91
      • 12.6.3.8 Instruction Width Selection

        93
    • 12.6.4 Memory Access Instructions

      94
      • 12.6.4.1 ADR

        95
      • 12.6.4.2 LDR and STR, Immediate Offset

        96
      • 12.6.4.3 LDR and STR, Register Offset

        98
      • 12.6.4.4 LDR and STR, Unprivileged

        100
      • 12.6.4.5 LDR, PC-relative

        101
      • 12.6.4.6 LDM and STM

        102
      • 12.6.4.7 PUSH and POP

        104
      • 12.6.4.8 LDREX and STREX

        105
      • 12.6.4.9 CLREX

        106
    • 12.6.5 General Data Processing Instructions

      107
      • 12.6.5.1 ADD, ADC, SUB, SBC, and RSB

        109
      • 12.6.5.2 AND, ORR, EOR, BIC, and ORN

        111
      • 12.6.5.3 ASR, LSL, LSR, ROR, and RRX

        113
      • 12.6.5.4 CLZ

        114
      • 12.6.5.5 CMP and CMN

        115
      • 12.6.5.6 MOV and MVN

        116
      • 12.6.5.7 MOVT

        117
      • 12.6.5.8 REV, REV16, REVSH, and RBIT

        118
      • 12.6.5.9 SADD16 and SADD8

        119
      • 12.6.5.10 SHADD16 and SHADD8

        120
      • 12.6.5.11 SHASX and SHSAX

        121
      • 12.6.5.12 SHSUB16 and SHSUB8

        122
      • 12.6.5.13 SSUB16 and SSUB8

        123
      • 12.6.5.14 SASX and SSAX

        124
      • 12.6.5.15 TST and TEQ

        125
      • 12.6.5.16 UADD16 and UADD8

        126
      • 12.6.5.17 UASX and USAX

        127
      • 12.6.5.18 UHADD16 and UHADD8

        128
      • 12.6.5.19 UHASX and UHSAX

        129
      • 12.6.5.20 UHSUB16 and UHSUB8

        130
      • 12.6.5.21 SEL

        131
      • 12.6.5.22 USAD8

        132
      • 12.6.5.23 USADA8

        133
      • 12.6.5.24 USUB16 and USUB8

        134
    • 12.6.6 Multiply and Divide Instructions

      135
      • 12.6.6.1 MUL, MLA, and MLS

        136
      • 12.6.6.2 UMULL, UMAAL, UMLAL

        137
      • 12.6.6.3 SMLA and SMLAW

        138
      • 12.6.6.4 SMLAD

        140
      • 12.6.6.5 SMLAL and SMLALD

        141
      • 12.6.6.6 SMLSD and SMLSLD

        143
      • 12.6.6.7 SMMLA and SMMLS

        145
      • 12.6.6.8 SMMUL

        147
      • 12.6.6.9 SMUAD and SMUSD

        148
      • 12.6.6.10 SMUL and SMULW

        150
      • 12.6.6.11 UMULL, UMLAL, SMULL, and SMLAL

        152
      • 12.6.6.12 SDIV and UDIV

        153
    • 12.6.7 Saturating Instructions

      154
      • 12.6.7.1 SSAT and USAT

        155
      • 12.6.7.2 SSAT16 and USAT16

        156
      • 12.6.7.3 QADD and QSUB

        157
      • 12.6.7.4 QASX and QSAX

        159
      • 12.6.7.5 QDADD and QDSUB

        160
      • 12.6.7.6 UQASX and UQSAX

        161
      • 12.6.7.7 UQADD and UQSUB

        163
    • 12.6.8 Packing and Unpacking Instructions

      164
      • 12.6.8.1 PKHBT and PKHTB

        165
      • 12.6.8.2 SXT and UXT

        166
      • 12.6.8.3 SXTA and UXTA

        167
    • 12.6.9 Bitfield Instructions

      168
      • 12.6.9.1 BFC and BFI

        169
      • 12.6.9.2 SBFX and UBFX

        170
      • 12.6.9.3 SXT and UXT

        171
    • 12.6.10 Branch and Control Instructions

      172
      • 12.6.10.1 B, BL, BX, and BLX

        173
      • 12.6.10.2 CBZ and CBNZ

        175
      • 12.6.10.3 IT

        176
      • 12.6.10.4 TBB and TBH

        178
    • 12.6.11 Floating-point Instructions

      180
      • 12.6.11.1 VABS

        182
      • 12.6.11.2 VADD

        183
      • 12.6.11.3 VCMP, VCMPE

        184
      • 12.6.11.4 VCVT, VCVTR between Floating-point and Integer

        185
      • 12.6.11.5 VCVT between Floating-point and Fixed-point

        186
      • 12.6.11.6 VCVTB, VCVTT

        187
      • 12.6.11.7 VDIV

        188
      • 12.6.11.8 VFMA, VFMS

        189
      • 12.6.11.9 VFNMA, VFNMS

        190
      • 12.6.11.10 VLDM

        191
      • 12.6.11.11 VLDR

        192
      • 12.6.11.12 VLMA, VLMS

        193
      • 12.6.11.13 VMOV Immediate

        194
      • 12.6.11.14 VMOV Register

        195
      • 12.6.11.15 VMOV Scalar to ARM Core Register

        196
      • 12.6.11.16 VMOV ARM Core Register to Single Precision

        197
      • 12.6.11.17 VMOV Two ARM Core Registers to Two Single Precision

        198
      • 12.6.11.18 VMOV ARM Core Register to Scalar

        199
      • 12.6.11.19 VMRS

        200
      • 12.6.11.20 VMSR

        201
      • 12.6.11.21 VMUL

        202
      • 12.6.11.22 VNEG

        203
      • 12.6.11.23 VNMLA, VNMLS, VNMUL

        204
      • 12.6.11.24 VPOP

        205
      • 12.6.11.25 VPUSH

        206
      • 12.6.11.26 VSQRT

        207
      • 12.6.11.27 VSTM

        208
      • 12.6.11.28 VSTR

        209
      • 12.6.11.29 VSUB

        210
    • 12.6.12 Miscellaneous Instructions

      211
      • 12.6.12.1 BKPT

        212
      • 12.6.12.2 CPS

        212
      • 12.6.12.3 DMB

        213
      • 12.6.12.4 DSB

        214
      • 12.6.12.5 ISB

        214
      • 12.6.12.6 MRS

        215
      • 12.6.12.7 MSR

        215
      • 12.6.12.8 NOP

        216
      • 12.6.12.9 SEV

        217
      • 12.6.12.10 SVC

        217
      • 12.6.12.11 WFE

        218
      • 12.6.12.12 WFI

        218
  • 12.7 Cortex-M4 Core Peripherals

    219
    • 12.7.1 Peripherals

      219
    • 12.7.2 Address Map

      219
  • 12.8 Nested Vectored Interrupt Controller (NVIC)

    220
    • 12.8.1 Level-sensitive Interrupts

      220
      • 12.8.1.1 Hardware and Software Control of Interrupts

        220
    • 12.8.2 NVIC Design Hints and Tips

      220
      • 12.8.2.1 NVIC Programming Hints

        221
    • 12.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface

      223
      • 12.8.3.1 Interrupt Set-enable Registers

        224
      • 12.8.3.2 Interrupt Clear-enable Registers

        225
      • 12.8.3.3 Interrupt Set-pending Registers

        226
      • 12.8.3.4 Interrupt Clear-pending Registers

        227
      • 12.8.3.5 Interrupt Active Bit Registers

        228
      • 12.8.3.6 Interrupt Priority Registers

        229
      • 12.8.3.7 Software Trigger Interrupt Register

        230
  • 12.9 System Control Block (SCB)

    231
    • 12.9.1 System Control Block (SCB) User Interface

      232
      • 12.9.1.1 Auxiliary Control Register

        233
      • 12.9.1.2 CPUID Base Register

        234
      • 12.9.1.3 Interrupt Control and State Register

        235
      • 12.9.1.4 Vector Table Offset Register

        237
      • 12.9.1.5 Application Interrupt and Reset Control Register

        238
      • 12.9.1.6 System Control Register

        240
      • 12.9.1.7 Configuration and Control Register

        241
      • 12.9.1.8 System Handler Priority Registers

        243
      • 12.9.1.9 System Handler Priority Register 1

        244
      • 12.9.1.10 System Handler Priority Register 2

        245
      • 12.9.1.11 System Handler Priority Register 3

        246
      • 12.9.1.12 System Handler Control and State Register

        247
      • 12.9.1.13 Configurable Fault Status Register

        250
      • 12.9.1.14 Configurable Fault Status Register (Byte Access)

        254
      • 12.9.1.15 Hard Fault Status Register

        255
      • 12.9.1.16 MemManage Fault Address Register

        256
      • 12.9.1.17 Bus Fault Address Register

        257
  • 12.10 System Timer (SysTick)

    258
    • 12.10.1 System Timer (SysTick) User Interface

      259
      • 12.10.1.1 SysTick Control and Status

        260
      • 12.10.1.2 SysTick Reload Value Registers

        261
      • 12.10.1.3 SysTick Current Value Register

        262
      • 12.10.1.4 SysTick Calibration Value Register

        263
  • 12.11 Memory Protection Unit (MPU)

    264
    • 12.11.1 MPU Access Permission Attributes

      264
      • 12.11.1.1 MPU Mismatch

        266
      • 12.11.1.2 Updating an MPU Region

        266
      • 12.11.1.3 Updating an MPU Region Using Separate Words

        266
      • 12.11.1.4 Updating an MPU Region Using Multi-word Writes

        267
      • 12.11.1.5 Subregions

        268
      • 12.11.1.6 Example of SRD Use

        268
      • 12.11.1.7 MPU Design Hints And Tips

        268
    • 12.11.2 Memory Protection Unit (MPU) User Interface

      270
      • 12.11.2.1 MPU Type Register

        271
      • 12.11.2.2 MPU Control Register

        272
      • 12.11.2.3 MPU Region Number Register

        274
      • 12.11.2.4 MPU Region Base Address Register

        275
      • 12.11.2.5 MPU Region Attribute and Size Register

        276
      • 12.11.2.6 MPU Region Base Address Register Alias 1

        278
      • 12.11.2.7 MPU Region Attribute and Size Register Alias 1

        279
      • 12.11.2.8 MPU Region Base Address Register Alias 2

        281
      • 12.11.2.9 MPU Region Attribute and Size Register Alias 2

        282
      • 12.11.2.10 MPU Region Base Address Register Alias 3

        284
      • 12.11.2.11 MPU Region Attribute and Size Register Alias 3

        285
  • 12.12 Floating Point Unit (FPU)

    287
    • 12.12.1 Enabling the FPU

      287
    • 12.12.2 Floating Point Unit (FPU) User Interface

      288
      • 12.12.2.1 Coprocessor Access Control Register

        289
      • 12.12.2.2 Floating-point Context Control Register

        290
      • 12.12.2.3 Floating-point Context Address Register

        292
      • 12.12.2.4 Floating-point Status Control Register

        293
      • 12.12.2.5 Floating-point Default Status Control Register

        295
  • 12.13 Glossary

    296
• 13. Debug and Test Features

  301
  • 13.1 Description

    301
  • 13.2 Embedded Characteristics

    301
  • 13.3 Debug and Test Block Diagram

    302
  • 13.4 Application Examples

    303
    • 13.4.1 Debug Environment

      303
    • 13.4.2 Test Environment

      303
  • 13.5 Debug and Test Pin Description

    304
  • 13.6 Functional Description

    305
    • 13.6.1 Test Pin

      305
    • 13.6.2 NRST Pin

      305
    • 13.6.3 ERASE Pin

      305
    • 13.6.4 Debug Architecture

      305
    • 13.6.5 Serial Wire JTAG Debug Port (SWJ-DP) Pins

      306
      • 13.6.5.1 SW-DP and JTAG-DP Selection Mechanism

        307
    • 13.6.6 FPB (Flash Patch Breakpoint)

      307
    • 13.6.7 DWT (Data Watchpoint and Trace)

      307
    • 13.6.8 ITM (Instrumentation Trace Macrocell)

      307
      • 13.6.8.1 How to Configure the ITM

        308
      • 13.6.8.2 Asynchronous Mode

        308
      • 13.6.8.3 5.4.3. How to Configure the TPIU

        308
    • 13.6.9 IEEE® 1149.1 JTAG Boundary Scan

      308
      • 13.6.9.1 JTAG Boundary-scan Register

        309
    • 13.6.10 ID Code Register

      310
• 14. Reset Controller (RSTC)

  311
  • 14.1 Description

    311
  • 14.2 Embedded Characteristics

    311
  • 14.3 Block Diagram

    311
  • 14.4 Functional Description

    312
    • 14.4.1 Reset Controller Overview

      312
    • 14.4.2 NRST Manager

      312
      • 14.4.2.1 NRST Signal or Interrupt

        312
      • 14.4.2.2 NRST External Reset Control

        313
    • 14.4.3 Brownout Manager

      313
    • 14.4.4 Reset States

      313
      • 14.4.4.1 General Reset

        313
      • 14.4.4.2 Backup Reset

        314
      • 14.4.4.3 User Reset

        314
      • 14.4.4.4 Software Reset

        314
      • 14.4.4.5 Watchdog Reset

        315
    • 14.4.5 Reset State Priorities

      316
    • 14.4.6 Reset Controller Status Register

      317
  • 14.5 Reset Controller (RSTC) User Interface

    318
    • 14.5.1 Reset Controller Control Register

      319
    • 14.5.2 Reset Controller Status Register

      320
    • 14.5.3 Reset Controller Mode Register

      321
• 15. Real-time Timer (RTT)

  322
  • 15.1 Description

    322
  • 15.2 Embedded Characteristics

    322
  • 15.3 Block Diagram

    322
  • 15.4 Functional Description

    322
  • 15.5 Real-time Timer (RTT) User Interface

    325
    • 15.5.1 Real-time Timer Mode Register

      326
    • 15.5.2 Real-time Timer Alarm Register

      327
    • 15.5.3 Real-time Timer Value Register

      328
    • 15.5.4 Real-time Timer Status Register

      329
• 16. Real-time Clock (RTC)

  330
  • 16.1 Description

    330
  • 16.2 Embedded Characteristics

    330
  • 16.3 Block Diagram

    331
  • 16.4 Product Dependencies

    331
    • 16.4.1 Power Management

      331
    • 16.4.2 Interrupt

      331
  • 16.5 Functional Description

    331
    • 16.5.1 Reference Clock

      331
    • 16.5.2 Timing

      331
    • 16.5.3 Alarm

      332
    • 16.5.4 Error Checking when Programming

      332
    • 16.5.5 RTC Internal Free Running Counter Error Checking

      332
    • 16.5.6 Updating Time/Calendar

      333
    • 16.5.7 RTC Accurate Clock Calibration

      335
    • 16.5.8 Waveform Generation

      335
  • 16.6 Real-time Clock (RTC) User Interface

    337
    • 16.6.1 RTC Control Register

      338
    • 16.6.2 RTC Mode Register

      340
    • 16.6.3 RTC Time Register

      343
    • 16.6.4 RTC Calendar Register

      344
    • 16.6.5 RTC Time Alarm Register

      345
    • 16.6.6 RTC Calendar Alarm Register

      346
    • 16.6.7 RTC Status Register

      347
    • 16.6.8 RTC Status Clear Command Register

      349
    • 16.6.9 RTC Interrupt Enable Register

      350
    • 16.6.10 RTC Interrupt Disable Register

      351
    • 16.6.11 RTC Interrupt Mask Register

      352
    • 16.6.12 RTC Valid Entry Register

      353
• 17. Watchdog Timer (WDT)

  354
  • 17.1 Description

    354
  • 17.2 Embedded Characteristics

    354
  • 17.3 Block Diagram

    354
  • 17.4 Functional Description

    355
  • 17.5 Watchdog Timer (WDT) User Interface

    357
    • 17.5.1 Watchdog Timer Control Register

      358
    • 17.5.2 Watchdog Timer Mode Register

      359
    • 17.5.3 Watchdog Timer Status Register

      361
• 18. Reinforced Safety Watchdog Timer (RSWDT)

  362
  • 18.1 Description

    362
  • 18.2 Embedded Characteristics

    362
  • 18.3 Block Diagram

    363
  • 18.4 Functional Description

    364
  • 18.5 Reinforced Safety Watchdog Timer (RSWDT) User Interface

    366
    • 18.5.1 Reinforced Safety Watchdog Timer Control Register

      367
    • 18.5.2 Reinforced Safety Watchdog Timer Mode Register

      368
    • 18.5.3 Reinforced Safety Watchdog Timer Status Register

      370
• 19. Supply Controller (SUPC)

  371
  • 19.1 Description

    371
  • 19.2 Embedded Characteristics

    371
  • 19.3 Block Diagram

    372
  • 19.4 Supply Controller Functional Description

    373
    • 19.4.1 Supply Controller Overview

      373
    • 19.4.2 Slow Clock Generator

      374
    • 19.4.3 Core Voltage Regulator Control/Backup Low-power Mode

      374
    • 19.4.4 Supply Monitor

      374
    • 19.4.5 Backup Power Supply Reset

      375
      • 19.4.5.1 Raising the Backup Power Supply

        375
    • 19.4.6 Core Reset

      376
      • 19.4.6.1 Supply Monitor Reset

        376
      • 19.4.6.2 Brownout Detector Reset

        377
    • 19.4.7 Wake-up Sources

      377
      • 19.4.7.1 Force Wake-up

        377
      • 19.4.7.2 Wake-up Inputs

        378
      • 19.4.7.3 Low-power Tamper Detection and Anti-Tampering

        378
      • 19.4.7.4 Clock Alarms

        380
      • 19.4.7.5 Supply Monitor Detection

        380
    • 19.4.8 Register Write Protection

      380
    • 19.4.9 Register Bits in Backup Domain (VDDIO)

      381
  • 19.5 Supply Controller (SUPC) User Interface

    382
    • 19.5.1 System Controller (SYSC) User Interface

      382
    • 19.5.2 Supply Controller (SUPC) User Interface

      382
    • 19.5.3 Supply Controller Control Register

      383
    • 19.5.4 Supply Controller Supply Monitor Mode Register

      384
    • 19.5.5 Supply Controller Mode Register

      385
    • 19.5.6 Supply Controller Wake-up Mode Register

      386
    • 19.5.7 Supply Controller Wake-up Inputs Register

      388
    • 19.5.8 Supply Controller Status Register

      389
    • 19.5.9 System Controller Write Protection Mode Register

      391
• 20. General Purpose Backup Registers (GPBR)

  392
  • 20.1 Description

    392
  • 20.2 Embedded Characteristics

    392
  • 20.3 General Purpose Backup Registers (GPBR) User Interface

    393
    • 20.3.1 General Purpose Backup Register x

      394
• 21. Enhanced Embedded Flash Controller (EEFC)

  395
  • 21.1 Description

    395
  • 21.2 Embedded Characteristics

    395
  • 21.3 Product Dependencies

    395
    • 21.3.1 Power Management

      395
    • 21.3.2 Interrupt Sources

      395
  • 21.4 Functional Description

    395
    • 21.4.1 Embedded Flash Organization

      395
    • 21.4.2 Read Operations

      397
      • 21.4.2.1 128-bit or 64-bit Access Mode

        397
      • 21.4.2.2 Code Read Optimization

        397
      • 21.4.2.3 Code Loop Optimization

        398
      • 21.4.2.4 Data Read Optimization

        399
    • 21.4.3 Flash Commands

      399
      • 21.4.3.1 Get Flash Descriptor Command

        401
      • 21.4.3.2 Write Commands

        402
      • 21.4.3.3 Erase Commands

        406
      • 21.4.3.4 Lock Bit Protection

        407
      • 21.4.3.5 GPNVM Bit

        408
      • 21.4.3.6 Calibration Bit

        408
      • 21.4.3.7 Security Bit Protection

        409
      • 21.4.3.8 Unique Identifier

        409
      • 21.4.3.9 User Signature

        409
  • 21.5 Enhanced Embedded Flash Controller (EEFC) User Interface

    411
    • 21.5.1 EEFC Flash Mode Register

      412
    • 21.5.2 EEFC Flash Command Register

      413
    • 21.5.3 EEFC Flash Status Register

      415
    • 21.5.4 EEFC Flash Result Register

      416
• 22. Fast Flash Programming Interface (FFPI)

  417
  • 22.1 Description

    417
  • 22.2 Embedded Characteristics

    417
  • 22.3 Parallel Fast Flash Programming

    418
    • 22.3.1 Device Configuration

      418
    • 22.3.2 Signal Names

      419
    • 22.3.3 Entering Programming Mode

      420
    • 22.3.4 Programmer Handshaking

      420
      • 22.3.4.1 Write Handshaking

        420
      • 22.3.4.2 Read Handshaking

        421
    • 22.3.5 Device Operations

      422
      • 22.3.5.1 Flash Read Command

        423
      • 22.3.5.2 Flash Write Command

        423
      • 22.3.5.3 Flash Full Erase Command

        424
      • 22.3.5.4 Flash Lock Commands

        424
      • 22.3.5.5 Flash General-purpose NVM Commands

        424
      • 22.3.5.6 Flash Security Bit Command

        425
      • 22.3.5.7 Memory Write Command

        425
      • 22.3.5.8 Get Version Command

        426
• 23. Cortex M Cache Controller (CMCC)

  427
  • 23.1 Description

    427
  • 23.2 Embedded Characteristics

    427
  • 23.3 Block Diagram

    428
  • 23.4 Functional Description

    428
    • 23.4.1 Cache Operation

      428
    • 23.4.2 Cache Maintenance

      428
      • 23.4.2.1 Cache Invalidate by Line Operation

        428
      • 23.4.2.2 Cache Invalidate All Operation

        429
    • 23.4.3 Cache Performance Monitoring

      429
  • 23.5 Cortex M Cache Controller (CMCC) User Interface

    430
    • 23.5.1 Cache Controller Type Register

      431
    • 23.5.2 Cache Controller Configuration Register

      433
    • 23.5.3 Cache Controller Control Register

      434
    • 23.5.4 Cache Controller Status Register

      435
    • 23.5.5 Cache Controller Maintenance Register 0

      436
    • 23.5.6 Cache Controller Maintenance Register 1

      437
    • 23.5.7 Cache Controller Monitor Configuration Register

      438
    • 23.5.8 Cache Controller Monitor Enable Register

      439
    • 23.5.9 Cache Controller Monitor Control Register

      440
    • 23.5.10 Cache Controller Monitor Status Register

      441
• 24. SAM-BA Boot Program for SAM4E Microcontrollers

  442
  • 24.1 Description

    442
  • 24.2 Embedded Characteristics

    442
  • 24.3 Hardware and Software Constraints

    442
  • 24.4 Flow Diagram

    443
  • 24.5 Device Initialization

    443
  • 24.6 SAM-BA Monitor

    444
    • 24.6.1 UART0 Serial Port

      445
    • 24.6.2 Xmodem Protocol

      445
    • 24.6.3 USB Device Port

      445
      • 24.6.3.1 Enumeration Process

        446
      • 24.6.3.2 Communication Endpoints

        446
    • 24.6.4 In Application Programming (IAP) Feature

      447
• 25. Bus Matrix (MATRIX)

  448
  • 25.1 Description

    448
  • 25.2 Embedded Characteristics

    448
    • 25.2.1 Matrix Masters

      448
    • 25.2.2 Matrix Slaves

      448
    • 25.2.3 Master to Slave Access

      449
  • 25.3 Memory Mapping

    450
  • 25.4 Special Bus Granting Mechanism

    450
  • 25.5 No Default Master

    450
  • 25.6 Last Access Master

    451
  • 25.7 Fixed Default Master

    451
  • 25.8 Arbitration

    451
    • 25.8.1 Arbitration Scheduling

      451
      • 25.8.1.1 Undefined Length Burst Arbitration

        452
      • 25.8.1.2 Slot Cycle Limit Arbitration

        452
    • 25.8.2 Arbitration Priority Scheme

      452
      • 25.8.2.1 Fixed Priority Arbitration

        453
      • 25.8.2.2 Round-Robin Arbitration

        453
  • 25.9 System I/O Configuration

    453
  • 25.10 SMC NAND Flash Chip Select Configuration

    453
  • 25.11 Write Protect Registers

    454
  • 25.12 Bus Matrix (MATRIX) User Interface

    455
    • 25.12.1 Bus Matrix Master Configuration Registers

      457
    • 25.12.2 Bus Matrix Slave Configuration Registers

      458
    • 25.12.3 Bus Matrix Priority Registers A For Slaves

      460
    • 25.12.4 Bus Matrix Master Remap Control Register

      461
    • 25.12.5 System I/O Configuration Register

      462
    • 25.12.6 SMC NAND Flash Chip Select Configuration Register

      463
    • 25.12.7 Write Protect Mode Register

      464
    • 25.12.8 Write Protect Status Register

      465
• 26. DMA Controller (DMAC)

  466
  • 26.1 Description

    466
  • 26.2 Embedded Characteristics

    466
  • 26.3 DMA Controller Peripheral Connections

    467
  • 26.4 Block Diagram

    468
  • 26.5 Functional Description

    468
    • 26.5.1 Basic Definitions

      468
    • 26.5.2 Memory Peripherals

      471
    • 26.5.3 Handshaking Interface

      471
      • 26.5.3.1 Software Handshaking

        471
    • 26.5.4 DMAC Transfer Types

      472
      • 26.5.4.1 Multi-buffer Transfers

        472
      • 26.5.4.2 Programming DMAC for Multiple Buffer Transfers

        473
      • 26.5.4.3 Ending Multi-buffer Transfers

        474
    • 26.5.5 Programming a Channel

      474
      • 26.5.5.1 Programming Examples

        474
    • 26.5.6 Disabling a Channel Prior to Transfer Completion

      481
      • 26.5.6.1 Abnormal Transfer Termination

        482
  • 26.6 DMAC Software Requirements

    482
  • 26.7 Write Protection Registers

    484
  • 26.8 DMA Controller (DMAC) User Interface

    485
    • 26.8.1 DMAC Global Configuration Register

      486
    • 26.8.2 DMAC Enable Register

      487
    • 26.8.3 DMAC Software Single Request Register

      488
    • 26.8.4 DMAC Software Chunk Transfer Request Register

      489
    • 26.8.5 DMAC Software Last Transfer Flag Register

      490
    • 26.8.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register

      491
    • 26.8.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register

      492
    • 26.8.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register

      493
    • 26.8.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register

      494
    • 26.8.10 DMAC Channel Handler Enable Register

      495
    • 26.8.11 DMAC Channel Handler Disable Register

      496
    • 26.8.12 DMAC Channel Handler Status Register

      497
    • 26.8.13 DMAC Channel x [x = 0..3] Source Address Register

      498
    • 26.8.14 DMAC Channel x [x = 0..3] Destination Address Register

      499
    • 26.8.15 DMAC Channel x [x = 0..3] Descriptor Address Register

      500
    • 26.8.16 DMAC Channel x [x = 0..3] Control A Register

      501
    • 26.8.17 DMAC Channel x [x = 0..3] Control B Register

      502
    • 26.8.18 DMAC Channel x [x = 0..3] Configuration Register

      504
    • 26.8.19 DMAC Write Protect Mode Register

      506
    • 26.8.20 DMAC Write Protect Status Register

      507
• 27. Peripheral DMA Controller (PDC)

  508
  • 27.1 Description

    508
  • 27.2 Embedded Characteristics

    508
  • 27.3 Peripheral DMA Controller Connections

    509
    • 27.3.1 Peripheral DMA Controller 0 (PDC0)

      509
    • 27.3.2 Peripheral DMA Controller 1 (PDC1)

      510
  • 27.4 Block Diagram

    511
  • 27.5 Functional Description

    512
    • 27.5.1 Configuration

      512
    • 27.5.2 Memory Pointers

      512
    • 27.5.3 Transfer Counters

      512
    • 27.5.4 Data Transfers

      513
    • 27.5.5 PDC Flags and Peripheral Status Register

      513
      • 27.5.5.1 Receive Transfer End

        513
      • 27.5.5.2 Transmit Transfer End

        513
      • 27.5.5.3 Receive Buffer Full

        513
      • 27.5.5.4 Transmit Buffer Empty

        513
  • 27.6 Peripheral DMA Controller (PDC) User Interface

    514
    • 27.6.1 Receive Pointer Register

      515
    • 27.6.2 Receive Counter Register

      516
    • 27.6.3 Transmit Pointer Register

      517
    • 27.6.4 Transmit Counter Register

      518
    • 27.6.5 Receive Next Pointer Register

      519
    • 27.6.6 Receive Next Counter Register

      520
    • 27.6.7 Transmit Next Pointer Register

      521
    • 27.6.8 Transmit Next Counter Register

      522
    • 27.6.9 Transfer Control Register

      523
    • 27.6.10 Transfer Status Register

      524
• 28. Static Memory Controller (SMC)

  525
  • 28.1 Description

    525
  • 28.2 Embedded Characteristics

    525
  • 28.3 I/O Lines Description

    526
  • 28.4 Product Dependencies

    526
    • 28.4.1 I/O Lines

      526
    • 28.4.2 Power Management

      526
  • 28.5 External Memory Mapping

    526
  • 28.6 Connection to External Devices

    527
    • 28.6.1 Data Bus Width

      527
      • 28.6.1.1 NAND Flash Support

        527
  • 28.7 Application Example

    529
    • 28.7.1 Implementation Examples

      529
      • 28.7.1.1 8-bit NAND Flash

        530
      • 28.7.1.2 NOR Flash

        531
  • 28.8 Standard Read and Write Protocols

    531
    • 28.8.1 Read Waveforms

      531
      • 28.8.1.1 NRD Waveform

        532
      • 28.8.1.2 NCS Waveform

        532
      • 28.8.1.3 Read Cycle

        532
      • 28.8.1.4 Null Delay Setup and Hold

        533
      • 28.8.1.5 Null Pulse

        533
    • 28.8.2 Read Mode

      533
      • 28.8.2.1 Read is Controlled by NRD (READ_MODE = 1):

        533
      • 28.8.2.2 Read is Controlled by NCS (READ_MODE = 0)

        534
    • 28.8.3 Write Waveforms

      535
      • 28.8.3.1 NWE Waveforms

        535
      • 28.8.3.2 NCS Waveforms

        535
      • 28.8.3.3 Write Cycle

        535
      • 28.8.3.4 Null Delay Setup and Hold

        536
      • 28.8.3.5 Null Pulse

        536
    • 28.8.4 Write Mode

      536
      • 28.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1):

        536
      • 28.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0)

        537
    • 28.8.5 Write Protected Registers

      537
    • 28.8.6 Coding Timing Parameters

      538
    • 28.8.7 Reset Values of Timing Parameters

      538
    • 28.8.8 Usage Restriction

      538
  • 28.9 Scrambling/Unscrambling Function

    539
  • 28.10 Automatic Wait States

    539
    • 28.10.1 Chip Select Wait States

      539
    • 28.10.2 Early Read Wait State

      540
    • 28.10.3 Reload User Configuration Wait State

      542
      • 28.10.3.1 User Procedure

        542
      • 28.10.3.2 Slow Clock Mode Transition

        543
    • 28.10.4 Read to Write Wait State

      543
  • 28.11 Data Float Wait States

    544
    • 28.11.1 READ_MODE

      544
    • 28.11.2 TDF Optimization Enabled (TDF_MODE = 1)

      545
    • 28.11.3 TDF Optimization Disabled (TDF_MODE = 0)

      546
  • 28.12 External Wait

    548
    • 28.12.1 Restriction

      548
    • 28.12.2 Frozen Mode

      549
    • 28.12.3 Ready Mode

      551
    • 28.12.4 NWAIT Latency and Read/Write Timings

      553
  • 28.13 Slow Clock Mode

    554
    • 28.13.1 Slow Clock Mode Waveforms

      554
    • 28.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode

      555
  • 28.14 Asynchronous Page Mode

    556
    • 28.14.1 Protocol and Timings in Page Mode

      556
    • 28.14.2 Page Mode Restriction

      557
    • 28.14.3 Sequential and Non-sequential Accesses

      557
  • 28.15 Static Memory Controller (SMC) User Interface

    559
    • 28.15.1 SMC Setup Register

      560
    • 28.15.2 SMC Pulse Register

      561
    • 28.15.3 SMC Cycle Register

      562
    • 28.15.4 SMC MODE Register

      563
    • 28.15.5 SMC OCMS Mode Register

      565
    • 28.15.6 SMC OCMS Key1 Register

      566
    • 28.15.7 SMC OCMS Key2 Register

      567
    • 28.15.8 SMC Write Protect Mode Register

      568
    • 28.15.9 SMC Write Protect Status Register

      569
• 29. Clock Generator

  570
  • 29.1 Description

    570
  • 29.2 Embedded Characteristics

    570
  • 29.3 Block Diagram

    571
  • 29.4 Slow Clock

    572
    • 29.4.1 Slow Clock RC Oscillator

      573
    • 29.4.2 Slow Clock Crystal Oscillator

      574
  • 29.5 Main Clock

    575
    • 29.5.1 Fast RC Oscillator

      576
    • 29.5.2 Fast RC Oscillator Clock Frequency Adjustment

      577
    • 29.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator

      578
    • 29.5.4 Main Clock Oscillator Selection

      579
    • 29.5.5 Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator

      580
    • 29.5.6 Software Sequence to Detect the Presence of Fast Crystal

      581
    • 29.5.7 Main Clock Frequency Counter

      582
  • 29.6 Divider and PLL Block

    583
    • 29.6.1 Divider and Phase Lock Loop Programming

      584
• 30. Power Management Controller (PMC)

  585
  • 30.1 Description

    585
  • 30.2 Embedded Characteristics

    585
  • 30.3 Block Diagram

    586
  • 30.4 Master Clock Controller

    586
  • 30.5 Processor Clock Controller

    587
  • 30.6 SysTick Clock

    587
  • 30.7 USB Clock Controller

    587
  • 30.8 Peripheral Clock Controller

    588
  • 30.9 Free-Running Processor Clock

    588
  • 30.10 Programmable Clock Output Controller

    588
  • 30.11 Fast Startup

    588
  • 30.12 Startup from Embedded Flash

    590
  • 30.13 Main Clock Failure Detector

    590
  • 30.14 Programming Sequence

    591
  • 30.15 Clock Switching Details

    594
    • 30.15.1 Master Clock Switching Timings

      594
    • 30.15.2 Clock Switching Waveforms

      595
  • 30.16 Register Write Protection

    597
  • 30.17 Power Management Controller (PMC) User Interface

    598
    • 30.17.1 PMC System Clock Enable Register

      600
    • 30.17.2 PMC System Clock Disable Register

      601
    • 30.17.3 PMC System Clock Status Register

      602
    • 30.17.4 PMC Peripheral Clock Enable Register 0

      603
    • 30.17.5 PMC Peripheral Clock Disable Register 0

      604
    • 30.17.6 PMC Peripheral Clock Status Register 0

      605
    • 30.17.7 PMC Clock Generator Main Oscillator Register

      606
    • 30.17.8 PMC Clock Generator Main Clock Frequency Register

      608
    • 30.17.9 PMC Clock Generator PLLA Register

      609
    • 30.17.10 PMC Master Clock Register

      610
    • 30.17.11 PMC USB Clock Register

      611
    • 30.17.12 PMC Programmable Clock Register

      612
    • 30.17.13 PMC Interrupt Enable Register

      613
    • 30.17.14 PMC Interrupt Disable Register

      614
    • 30.17.15 PMC Status Register

      615
    • 30.17.16 PMC Interrupt Mask Register

      617
    • 30.17.17 PMC Fast Startup Mode Register

      618
    • 30.17.18 PMC Fast Startup Polarity Register

      619
    • 30.17.19 PMC Fault Output Clear Register

      620
    • 30.17.20 PMC Write Protection Mode Register

      621
    • 30.17.21 PMC Write Protection Status Register

      622
    • 30.17.22 PMC Peripheral Clock Enable Register 1

      623
    • 30.17.23 PMC Peripheral Clock Disable Register 1

      624
    • 30.17.24 PMC Peripheral Clock Status Register 1

      625
    • 30.17.25 PMC Oscillator Calibration Register

      626
    • 30.17.26 PLL Maximum Multiplier Value Register

      627
• 31. Advanced Encryption Standard (AES)

  628
  • 31.1 Description

    628
  • 31.2 Embedded Characteristics

    628
  • 31.3 Product Dependencies

    629
    • 31.3.1 Power Management

      629
    • 31.3.2 Interrupt

      629
  • 31.4 Functional Description

    629
    • 31.4.1 Operation Modes

      629
    • 31.4.2 Double Input Buffer

      630
    • 31.4.3 Start Modes

      630
      • 31.4.3.1 Manual Mode

        630
      • 31.4.3.2 Auto Mode

        631
      • 31.4.3.3 DMA Mode

        631
    • 31.4.4 Last Output Data Mode

      631
      • 31.4.4.1 Manual and Auto Modes

        632
      • 31.4.4.2 DMA Mode

        632
  • 31.5 Security Features

    634
    • 31.5.1 Unspecified Register Access Detection

      634
  • 31.6 Advanced Encryption Standard (AES) User Interface

    635
    • 31.6.1 AES Control Register

      636
    • 31.6.2 AES Mode Register

      637
    • 31.6.3 AES Interrupt Enable Register

      640
    • 31.6.4 AES Interrupt Disable Register

      641
    • 31.6.5 AES Interrupt Mask Register

      642
    • 31.6.6 AES Interrupt Status Register

      643
    • 31.6.7 AES Key Word Register x

      644
    • 31.6.8 AES Input Data Register x

      645
    • 31.6.9 AES Output Data Register x

      646
    • 31.6.10 AES Initialization Vector Register x

      647
• 32. Chip Identifier (CHIPID)

  648
  • 32.1 Description

    648
  • 32.2 Embedded Characteristics

    648
  • 32.3 Chip Identifier (CHIPID) User Interface

    649
    • 32.3.1 Chip ID Register

      650
    • 32.3.2 Chip ID Extension Register

      653
• 33. Controller Area Network (CAN)

  654
  • 33.1 Description

    654
  • 33.2 Embedded Characteristics

    654
  • 33.3 Block Diagram

    655
  • 33.4 Application Block Diagram

    656
  • 33.5 I/O Lines Description

    656
  • 33.6 Product Dependencies

    656
    • 33.6.1 I/O Lines

      656
    • 33.6.2 Power Management

      656
    • 33.6.3 Interrupt

      657
  • 33.7 CAN Controller Features

    657
    • 33.7.1 CAN Protocol Overview

      657
    • 33.7.2 Mailbox Organization

      657
      • 33.7.2.1 Message Acceptance Procedure

        657
      • 33.7.2.2 Receive Mailbox

        658
      • 33.7.2.3 Transmit Mailbox

        659
    • 33.7.3 Time Management Unit

      660
    • 33.7.4 CAN 2.0 Standard Features

      660
      • 33.7.4.1 CAN Bit Timing Configuration

        660
        • CAN Bus Synchronization

          663
        • Autobaud Mode

          664
      • 33.7.4.2 Error Detection

        664
        • Fault Confinement

          665
        • Error Interrupt Handler

          665
      • 33.7.4.3 Overload

        666
    • 33.7.5 Low-power Mode

      666
      • 33.7.5.1 Enabling Low-power Mode

        666
      • 33.7.5.2 Disabling Low-power Mode

        667
  • 33.8 Functional Description

    668
    • 33.8.1 CAN Controller Initialization

      668
    • 33.8.2 CAN Controller Interrupt Handling

      669
    • 33.8.3 CAN Controller Message Handling

      670
      • 33.8.3.1 Receive Handling

        670
        • Simple Receive Mailbox

          670
        • Receive with Overwrite Mailbox

          671
        • Chaining Mailboxes

          671
      • 33.8.3.2 Transmission Handling

        673
      • 33.8.3.3 Remote Frame Handling

        674
        • Producer Configuration

          675
        • Consumer Configuration

          675
    • 33.8.4 CAN Controller Timing Modes

      676
      • 33.8.4.1 Timestamping Mode

        676
      • 33.8.4.2 Time Triggered Mode

        677
        • Synchronization by a Reference Message

          677
        • Transmitting within a Time Window

          677
        • Freezing the Internal Timer Counter

          677
    • 33.8.5 Write Protected Registers

      679
  • 33.9 Controller Area Network (CAN) User Interface

    680
    • 33.9.1 CAN Mode Register

      681
    • 33.9.2 CAN Interrupt Enable Register

      683
    • 33.9.3 CAN Interrupt Disable Register

      685
    • 33.9.4 CAN Interrupt Mask Register

      687
    • 33.9.5 CAN Status Register

      689
    • 33.9.6 CAN Baudrate Register

      692
    • 33.9.7 CAN Timer Register

      693
    • 33.9.8 CAN Timestamp Register

      694
    • 33.9.9 CAN Error Counter Register

      695
    • 33.9.10 CAN Transfer Command Register

      696
    • 33.9.11 CAN Abort Command Register

      697
    • 33.9.12 CAN Write Protection Mode Register

      698
    • 33.9.13 CAN Write Protection Status Register

      699
    • 33.9.14 CAN Message Mode Register

      700
    • 33.9.15 CAN Message Acceptance Mask Register

      701
    • 33.9.16 CAN Message ID Register

      702
    • 33.9.17 CAN Message Family ID Register

      703
    • 33.9.18 CAN Message Status Register

      704
    • 33.9.19 CAN Message Data Low Register

      707
    • 33.9.20 CAN Message Data High Register

      708
    • 33.9.21 CAN Message Control Register

      709
• 34. Parallel Input/Output Controller (PIO)

  711
  • 34.1 Description

    711
  • 34.2 Embedded Characteristics

    712
  • 34.3 Block Diagram

    713
  • 34.4 Product Dependencies

    715
    • 34.4.1 Pin Multiplexing

      715
    • 34.4.2 External Interrupt Lines

      715
    • 34.4.3 Power Management

      715
    • 34.4.4 Interrupt Generation

      715
  • 34.5 Functional Description

    716
    • 34.5.1 Pull-up and Pull-down Resistor Control

      716
    • 34.5.2 I/O Line or Peripheral Function Selection

      717
    • 34.5.3 Peripheral A or B or C or D Selection

      717
    • 34.5.4 Output Control

      718
    • 34.5.5 Synchronous Data Output

      718
    • 34.5.6 Multi-Drive Control (Open Drain)

      718
    • 34.5.7 Output Line Timings

      718
    • 34.5.8 Inputs

      719
    • 34.5.9 Input Glitch and Debouncing Filters

      719
    • 34.5.10 Input Edge/Level Interrupt

      720
    • 34.5.11 I/O Lines Lock

      723
    • 34.5.12 Programmable I/O Delays

      723
    • 34.5.13 Programmable Schmitt Trigger

      724
    • 34.5.14 Parallel Capture Mode

      724
      • 34.5.14.1 Overview

        724
      • 34.5.14.2 Functional Description

        724
      • 34.5.14.3 Restrictions

        727
      • 34.5.14.4 Programming Sequence

        727
        • Without PDC

          727
        • With PDC

          727
    • 34.5.15 I/O Lines Programming Example

      728
    • 34.5.16 Register Write Protection

      729
  • 34.6 Parallel Input/Output Controller (PIO) User Interface

    730
    • 34.6.1 PIO Enable Register

      733
    • 34.6.2 PIO Disable Register

      734
    • 34.6.3 PIO Status Register

      735
    • 34.6.4 PIO Output Enable Register

      736
    • 34.6.5 PIO Output Disable Register

      737
    • 34.6.6 PIO Output Status Register

      738
    • 34.6.7 PIO Input Filter Enable Register

      739
    • 34.6.8 PIO Input Filter Disable Register

      740
    • 34.6.9 PIO Input Filter Status Register

      741
    • 34.6.10 PIO Set Output Data Register

      742
    • 34.6.11 PIO Clear Output Data Register

      743
    • 34.6.12 PIO Output Data Status Register

      744
    • 34.6.13 PIO Pin Data Status Register

      745
    • 34.6.14 PIO Interrupt Enable Register

      746
    • 34.6.15 PIO Interrupt Disable Register

      747
    • 34.6.16 PIO Interrupt Mask Register

      748
    • 34.6.17 PIO Interrupt Status Register

      749
    • 34.6.18 PIO Multi-driver Enable Register

      750
    • 34.6.19 PIO Multi-driver Disable Register

      751
    • 34.6.20 PIO Multi-driver Status Register

      752
    • 34.6.21 PIO Pull-Up Disable Register

      753
    • 34.6.22 PIO Pull-Up Enable Register

      754
    • 34.6.23 PIO Pull-Up Status Register

      755
    • 34.6.24 PIO Peripheral ABCD Select Register 1

      756
    • 34.6.25 PIO Peripheral ABCD Select Register 2

      757
    • 34.6.26 PIO Input Filter Slow Clock Disable Register

      758
    • 34.6.27 PIO Input Filter Slow Clock Enable Register

      759
    • 34.6.28 PIO Input Filter Slow Clock Status Register

      760
    • 34.6.29 PIO Slow Clock Divider Debouncing Register

      761
    • 34.6.30 PIO Pad Pull-Down Disable Register

      762
    • 34.6.31 PIO Pad Pull-Down Enable Register

      763
    • 34.6.32 PIO Pad Pull-Down Status Register

      764
    • 34.6.33 PIO Output Write Enable Register

      765
    • 34.6.34 PIO Output Write Disable Register

      766
    • 34.6.35 PIO Output Write Status Register

      767
    • 34.6.36 PIO Additional Interrupt Modes Enable Register

      768
    • 34.6.37 PIO Additional Interrupt Modes Disable Register

      769
    • 34.6.38 PIO Additional Interrupt Modes Mask Register

      770
    • 34.6.39 PIO Edge Select Register

      771
    • 34.6.40 PIO Level Select Register

      772
    • 34.6.41 PIO Edge/Level Status Register

      773
    • 34.6.42 PIO Falling Edge/Low-Level Select Register

      774
    • 34.6.43 PIO Rising Edge/High-Level Select Register

      775
    • 34.6.44 PIO Fall/Rise - Low/High Status Register

      776
    • 34.6.45 PIO Lock Status Register

      777
    • 34.6.46 PIO Write Protection Mode Register

      778
    • 34.6.47 PIO Write Protection Status Register

      779
    • 34.6.48 PIO Schmitt Trigger Register

      780
    • 34.6.49 PIO I/O Delay Register

      781
    • 34.6.50 PIO Parallel Capture Mode Register

      782
    • 34.6.51 PIO Parallel Capture Interrupt Enable Register

      783
    • 34.6.52 PIO Parallel Capture Interrupt Disable Register

      784
    • 34.6.53 PIO Parallel Capture Interrupt Mask Register

      785
    • 34.6.54 PIO Parallel Capture Interrupt Status Register

      786
    • 34.6.55 PIO Parallel Capture Reception Holding Register

      787
• 35. Serial Peripheral Interface (SPI)

  788
  • 35.1 Description

    788
  • 35.2 Embedded Characteristics

    789
  • 35.3 Block Diagram

    790
  • 35.4 Application Block Diagram

    791
  • 35.5 Signal Description

    791
  • 35.6 Product Dependencies

    791
    • 35.6.1 I/O Lines

      791
    • 35.6.2 Power Management

      792
    • 35.6.3 Interrupt

      792
    • 35.6.4 Peripheral DMA Controller (PDC) or Direct Memory Access Controller (DMAC)

      792
  • 35.7 Functional Description

    792
    • 35.7.1 Modes of Operation

      792
    • 35.7.2 Data Transfer

      793
    • 35.7.3 Master Mode Operations

      794
      • 35.7.3.1 Master Mode Block Diagram

        795
      • 35.7.3.2 Master Mode Flow Diagram

        796
      • 35.7.3.3 Clock Generation

        798
      • 35.7.3.4 Transfer Delays

        798
      • 35.7.3.5 Peripheral Selection

        799
      • 35.7.3.6 SPI Peripheral DMA Controller (PDC)

        799
      • 35.7.3.7 SPI Direct Access Memory Controller (DMAC)

        800
      • 35.7.3.8 Peripheral Chip Select Decoding

        800
      • 35.7.3.9 Peripheral Deselection without DMA nor PDC

        801
      • 35.7.3.10 Peripheral Deselection with DMA or PDC

        802
      • 35.7.3.11 Mode Fault Detection

        803
    • 35.7.4 SPI Slave Mode

      804
    • 35.7.5 Register Write Protection

      805
  • 35.8 Serial Peripheral Interface (SPI) User Interface

    806
    • 35.8.1 SPI Control Register

      807
    • 35.8.2 SPI Mode Register

      808
    • 35.8.3 SPI Receive Data Register

      810
    • 35.8.4 SPI Transmit Data Register

      811
    • 35.8.5 SPI Status Register

      812
    • 35.8.6 SPI Interrupt Enable Register

      814
    • 35.8.7 SPI Interrupt Disable Register

      815
    • 35.8.8 SPI Interrupt Mask Register

      816
    • 35.8.9 SPI Chip Select Register

      817
    • 35.8.10 SPI Write Protection Mode Register

      820
    • 35.8.11 SPI Write Protection Status Register

      821
• 36. Two-wire Interface (TWI)

  822
  • 36.1 Description

    822
  • 36.2 Embedded Characteristics

    822
  • 36.3 List of Abbreviations

    823
  • 36.4 Block Diagram

    823
  • 36.5 Application Block Diagram

    824
    • 36.5.1 I/O Lines Description

      824
  • 36.6 Product Dependencies

    824
    • 36.6.1 I/O Lines

      824
    • 36.6.2 Power Management

      824
    • 36.6.3 Interrupt

      825
  • 36.7 Functional Description

    825
    • 36.7.1 Transfer Format

      825
    • 36.7.2 Modes of Operation

      825
    • 36.7.3 Master Mode

      826
      • 36.7.3.1 Definition

        826
      • 36.7.3.2 Application Block Diagram

        826
      • 36.7.3.3 Programming Master Mode

        826
      • 36.7.3.4 Master Transmitter Mode

        826
      • 36.7.3.5 Master Receiver Mode

        828
      • 36.7.3.6 Internal Address

        829
      • 36.7.3.7 Using the Peripheral DMA Controller (PDC)

        831
      • 36.7.3.8 SMBus Quick Command (Master Mode Only)

        832
      • 36.7.3.9 Read/Write Flowcharts

        832
    • 36.7.4 Multi-master Mode

      839
      • 36.7.4.1 Definition

        839
      • 36.7.4.2 Different Multi-master Modes

        839
    • 36.7.5 Slave Mode

      842
      • 36.7.5.1 Definition

        842
      • 36.7.5.2 Application Block Diagram

        842
      • 36.7.5.3 Programming Slave Mode

        842
      • 36.7.5.4 Receiving Data

        842
      • 36.7.5.5 Data Transfer

        843
      • 36.7.5.6 Using the Peripheral DMA Controller (PDC) in Slave Mode

        847
      • 36.7.5.7 Read Write Flowcharts

        847
    • 36.7.6 Register Write Protection

      848
  • 36.8 Two-wire Interface (TWI) User Interface

    849
    • 36.8.1 TWI Control Register

      850
    • 36.8.2 TWI Master Mode Register

      852
    • 36.8.3 TWI Slave Mode Register

      853
    • 36.8.4 TWI Internal Address Register

      854
    • 36.8.5 TWI Clock Waveform Generator Register

      855
    • 36.8.6 TWI Status Register

      856
    • 36.8.7 TWI Interrupt Enable Register

      859
    • 36.8.8 TWI Interrupt Disable Register

      860
    • 36.8.9 TWI Interrupt Mask Register

      861
    • 36.8.10 TWI Receive Holding Register

      862
    • 36.8.11 TWI Transmit Holding Register

      863
    • 36.8.12 TWI Write Protection Mode Register

      864
    • 36.8.13 TWI Write Protection Status Register

      865
• 37. Universal Asynchronous Receiver Transmitter (UART)

  866
  • 37.1 Description

    866
  • 37.2 Embedded Characteristics

    866
  • 37.3 Block Diagram

    866
  • 37.4 Product Dependencies

    867
    • 37.4.1 I/O Lines

      867
    • 37.4.2 Power Management

      867
    • 37.4.3 Interrupt Source

      867
  • 37.5 UART Operations

    867
    • 37.5.1 Baud Rate Generator

      867
    • 37.5.2 Receiver

      868
      • 37.5.2.1 Receiver Reset, Enable and Disable

        868
      • 37.5.2.2 Start Detection and Data Sampling

        868
      • 37.5.2.3 Receiver Ready

        869
      • 37.5.2.4 Receiver Overrun

        869
      • 37.5.2.5 Parity Error

        869
      • 37.5.2.6 Receiver Framing Error

        870
    • 37.5.3 Transmitter

      870
      • 37.5.3.1 Transmitter Reset, Enable and Disable

        870
      • 37.5.3.2 Transmit Format

        870
      • 37.5.3.3 Transmitter Control

        871
    • 37.5.4 Peripheral DMA Controller (PDC)

      871
    • 37.5.5 Register Write Protection

      872
    • 37.5.6 Test Modes

      872
  • 37.6 Universal Asynchronous Receiver Transmitter (UART) User Interface

    873
    • 37.6.1 UART Control Register

      874
    • 37.6.2 UART Mode Register

      875
    • 37.6.3 UART Interrupt Enable Register

      876
    • 37.6.4 UART Interrupt Disable Register

      877
    • 37.6.5 UART Interrupt Mask Register

      878
    • 37.6.6 UART Status Register

      879
    • 37.6.7 UART Receiver Holding Register

      881
    • 37.6.8 UART Transmit Holding Register

      882
    • 37.6.9 UART Baud Rate Generator Register

      883
    • 37.6.10 UART Write Protection Mode Register

      884
• 38. Universal Synchronous Asynchronous Receiver Transmitter (USART)

  885
  • 38.1 Description

    885
  • 38.2 Embedded Characteristics

    885
  • 38.3 Block Diagram

    886
  • 38.4 Application Block Diagram

    887
  • 38.5 I/O Lines Description

    888
  • 38.6 Product Dependencies

    889
    • 38.6.1 I/O Lines

      889
    • 38.6.2 Power Management

      889
    • 38.6.3 Interrupt

      889
  • 38.7 Functional Description

    890
    • 38.7.1 Baud Rate Generator

      890
      • 38.7.1.1 Baud Rate in Asynchronous Mode

        890
        • Baud Rate Calculation Example

          891
      • 38.7.1.2 Fractional Baud Rate in Asynchronous Mode

        891
      • 38.7.1.3 Baud Rate in Synchronous Mode or SPI Mode

        892
      • 38.7.1.4 Baud Rate in ISO 7816 Mode

        892
    • 38.7.2 Receiver and Transmitter Control

      894
    • 38.7.3 Synchronous and Asynchronous Modes

      894
      • 38.7.3.1 Transmitter Operations

        894
      • 38.7.3.2 Manchester Encoder

        895
        • Drift Compensation

          897
      • 38.7.3.3 Asynchronous Receiver

        897
      • 38.7.3.4 Manchester Decoder

        898
      • 38.7.3.5 Radio Interface: Manchester Encoded USART Application

        900
      • 38.7.3.6 Synchronous Receiver

        901
      • 38.7.3.7 Receiver Operations

        902
      • 38.7.3.8 Parity

        902
      • 38.7.3.9 Multidrop Mode

        903
      • 38.7.3.10 Transmitter Timeguard

        903
      • 38.7.3.11 Receiver Time-out

        904
      • 38.7.3.12 Framing Error

        906
      • 38.7.3.13 Transmit Break

        906
      • 38.7.3.14 Receive Break

        907
      • 38.7.3.15 Hardware Handshaking

        907
    • 38.7.4 ISO7816 Mode

      908
      • 38.7.4.1 ISO7816 Mode Overview

        908
      • 38.7.4.2 Protocol T = 0

        909
        • Receive Error Counter

          909
        • Receive NACK Inhibit

          909
        • Transmit Character Repetition

          909
        • Disable Successive Receive NACK

          910
      • 38.7.4.3 Protocol T = 1

        910
    • 38.7.5 IrDA Mode

      910
      • 38.7.5.1 IrDA Modulation

        911
      • 38.7.5.2 IrDA Baud Rate

        911
      • 38.7.5.3 IrDA Demodulator

        912
    • 38.7.6 RS485 Mode

      912
    • 38.7.7 Modem Mode

      914
    • 38.7.8 SPI Mode

      915
      • 38.7.8.1 Modes of Operation

        915
      • 38.7.8.2 Baud Rate

        915
      • 38.7.8.3 Data Transfer

        916
      • 38.7.8.4 Receiver and Transmitter Control

        917
      • 38.7.8.5 Character Transmission

        917
      • 38.7.8.6 Character Reception

        918
      • 38.7.8.7 Receiver Timeout

        918
    • 38.7.9 Test Modes

      918
      • 38.7.9.1 Normal Mode

        918
      • 38.7.9.2 Automatic Echo Mode

        919
      • 38.7.9.3 Local Loopback Mode

        919
      • 38.7.9.4 Remote Loopback Mode

        919
    • 38.7.10 Register Write Protection

      920
  • 38.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface

    921
    • 38.8.1 USART Control Register

      922
    • 38.8.2 USART Control Register (SPI_MODE)

      925
    • 38.8.3 USART Mode Register

      927
    • 38.8.4 USART Mode Register (SPI_MODE)

      930
    • 38.8.5 USART Interrupt Enable Register

      932
    • 38.8.6 USART Interrupt Enable Register (SPI_MODE)

      934
    • 38.8.7 USART Interrupt Disable Register

      935
    • 38.8.8 USART Interrupt Disable Register (SPI_MODE)

      937
    • 38.8.9 USART Interrupt Mask Register

      938
    • 38.8.10 USART Interrupt Mask Register (SPI_MODE)

      940
    • 38.8.11 USART Channel Status Register

      941
    • 38.8.12 USART Channel Status Register (SPI_MODE)

      944
    • 38.8.13 USART Receive Holding Register

      945
    • 38.8.14 USART Transmit Holding Register

      946
    • 38.8.15 USART Baud Rate Generator Register

      947
    • 38.8.16 USART Receiver Time-out Register

      948
    • 38.8.17 USART Transmitter Timeguard Register

      949
    • 38.8.18 USART FI DI RATIO Register

      950
    • 38.8.19 USART Number of Errors Register

      951
    • 38.8.20 USART IrDA FILTER Register

      952
    • 38.8.21 USART Manchester Configuration Register

      953
    • 38.8.22 USART Write Protection Mode Register

      955
    • 38.8.23 USART Write Protection Status Register

      956
• 39. Timer Counter (TC)

  957
  • 39.1 Description

    957
  • 39.2 Embedded Characteristics

    957
  • 39.3 Block Diagram

    958
  • 39.4 Pin Name List

    959
  • 39.5 Product Dependencies

    959
    • 39.5.1 I/O Lines

      959
    • 39.5.2 Power Management

      960
    • 39.5.3 Interrupt

      960
    • 39.5.4 Synchronization Inputs from PWM

      960
    • 39.5.5 Fault Output

      960
  • 39.6 Functional Description

    960
    • 39.6.1 TC Description

      960
    • 39.6.2 32-bit Counter

      960
    • 39.6.3 Clock Selection

      961
    • 39.6.4 Clock Control

      962
    • 39.6.5 TC Operating Modes

      963
    • 39.6.6 Trigger

      963
    • 39.6.7 Capture Operating Mode

      964
    • 39.6.8 Capture Registers A and B

      964
    • 39.6.9 Transfer with PDC

      964
    • 39.6.10 Trigger Conditions

      965
    • 39.6.11 Waveform Operating Mode

      967
    • 39.6.12 Waveform Selection

      967
      • 39.6.12.1 WAVSEL = 00

        969
      • 39.6.12.2 WAVSEL = 10

        970
      • 39.6.12.3 WAVSEL = 01

        971
      • 39.6.12.4 WAVSEL = 11

        972
    • 39.6.13 External Event/Trigger Conditions

      973
    • 39.6.14 Synchronization with PWM

      973
    • 39.6.15 Output Controller

      974
    • 39.6.16 Quadrature Decoder Logic

      975
      • 39.6.16.1 Description

        975
      • 39.6.16.2 Input Pre-processing

        976
      • 39.6.16.3 Direction Status and Change Detection

        979
      • 39.6.16.4 Position and Rotation Measurement

        980
      • 39.6.16.5 Speed Measurement

        981
      • 39.6.16.6 Missing Pulse Detection and Auto-correction

        981
    • 39.6.17 2-bit Gray Up/Down Counter for Stepper Motor

      982
    • 39.6.18 Register Write Protection

      982
    • 39.6.19 Fault Mode

      982
  • 39.7 Timer Counter (TC) User Interface

    984
    • 39.7.1 TC Channel Control Register

      985
    • 39.7.2 TC Channel Mode Register: Capture Mode

      986
    • 39.7.3 TC Channel Mode Register: Waveform Mode

      989
    • 39.7.4 TC Stepper Motor Mode Register

      993
    • 39.7.5 TC Register AB

      994
    • 39.7.6 TC Counter Value Register

      995
    • 39.7.7 TC Register A

      996
    • 39.7.8 TC Register B

      997
    • 39.7.9 TC Register C

      998
    • 39.7.10 TC Status Register

      999
    • 39.7.11 TC Interrupt Enable Register

      1001
    • 39.7.12 TC Interrupt Disable Register

      1003
    • 39.7.13 TC Interrupt Mask Register

      1005
    • 39.7.14 TC Extended Mode Register

      1007
    • 39.7.15 TC Block Control Register

      1008
    • 39.7.16 TC Block Mode Register

      1009
    • 39.7.17 TC QDEC Interrupt Enable Register

      1011
    • 39.7.18 TC QDEC Interrupt Disable Register

      1012
    • 39.7.19 TC QDEC Interrupt Mask Register

      1013
    • 39.7.20 TC QDEC Interrupt Status Register

      1014
    • 39.7.21 TC Fault Mode Register

      1015
    • 39.7.22 TC Write Protection Mode Register

      1016
• 40. Pulse Width Modulation Controller (PWM)

  1017
  • 40.1 Description

    1017
  • 40.2 Embedded Characteristics

    1018
  • 40.3 Block Diagram

    1019
  • 40.4 I/O Lines Description

    1019
  • 40.5 Product Dependencies

    1020
    • 40.5.1 I/O Lines

      1020
    • 40.5.2 Power Management

      1021
    • 40.5.3 Interrupt Sources

      1021
    • 40.5.4 Fault Inputs

      1021
  • 40.6 Functional Description

    1023
    • 40.6.1 PWM Clock Generator

      1023
    • 40.6.2 PWM Channel

      1024
      • 40.6.2.1 Channel Block Diagram

        1024
      • 40.6.2.2 Comparator

        1025
      • 40.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor

        1027
      • 40.6.2.4 Dead-Time Generator

        1028
      • 40.6.2.5 Output Override

        1029
      • 40.6.2.6 Fault Protection

        1030
      • 40.6.2.7 Spread Spectrum Counter

        1032
      • 40.6.2.8 Additional Edges

        1032
      • 40.6.2.9 Synchronous Channels

        1033
      • 40.6.2.10 Update Time for Double-Buffering Registers

        1039
    • 40.6.3 PWM Comparison Units

      1040
    • 40.6.4 PWM Event Lines

      1041
    • 40.6.5 PWM Controller Operations

      1042
      • 40.6.5.1 Initialization

        1042
      • 40.6.5.2 Source Clock Selection Criteria

        1043
      • 40.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times

        1043
      • 40.6.5.4 Changing the Synchronous Channels Update Period

        1044
      • 40.6.5.5 Changing the Comparison Value and the Comparison Configuration

        1045
      • 40.6.5.6 Interrupts

        1046
    • 40.6.6 Register Write Protection

      1046
  • 40.7 Pulse Width Modulation Controller (PWM) User Interface

    1048
    • 40.7.1 PWM Clock Register

      1051
    • 40.7.2 PWM Enable Register

      1052
    • 40.7.3 PWM Disable Register

      1053
    • 40.7.4 PWM Status Register

      1054
    • 40.7.5 PWM Interrupt Enable Register 1

      1055
    • 40.7.6 PWM Interrupt Disable Register 1

      1056
    • 40.7.7 PWM Interrupt Mask Register 1

      1057
    • 40.7.8 PWM Interrupt Status Register 1

      1058
    • 40.7.9 PWM Sync Channels Mode Register

      1059
    • 40.7.10 PWM DMA Register

      1060
    • 40.7.11 PWM Sync Channels Update Control Register

      1061
    • 40.7.12 PWM Sync Channels Update Period Register

      1062
    • 40.7.13 PWM Sync Channels Update Period Update Register

      1063
    • 40.7.14 PWM Interrupt Enable Register 2

      1064
    • 40.7.15 PWM Interrupt Disable Register 2

      1065
    • 40.7.16 PWM Interrupt Mask Register 2

      1066
    • 40.7.17 PWM Interrupt Status Register 2

      1067
    • 40.7.18 PWM Output Override Value Register

      1068
    • 40.7.19 PWM Output Selection Register

      1069
    • 40.7.20 PWM Output Selection Set Register

      1070
    • 40.7.21 PWM Output Selection Clear Register

      1071
    • 40.7.22 PWM Output Selection Set Update Register

      1072
    • 40.7.23 PWM Output Selection Clear Update Register

      1073
    • 40.7.24 PWM Fault Mode Register

      1074
      • 0: The fault y is active until the fault condition is removed at the peripheral(1) level.

        1074
      • 1: The fault y stays active until the fault condition is removed at the peripheral(1) level AND until it is cleared in the PWM Fault Clear Register.

        1074
      • 0: The fault input y is not filtered.

        1074
      • 1: The fault input y is filtered.

        1074
    • 40.7.25 PWM Fault Status Register

      1075
      • 0: The current sampled value of the fault input y is 0 (after filtering if enabled).

        1075
      • 1: The current sampled value of the fault input y is 1 (after filtering if enabled).

        1075
      • 0: The fault y is not currently active.

        1075
      • 1: The fault y is currently active.

        1075
    • 40.7.26 PWM Fault Clear Register

      1076
      • 0: No effect.

        1076
      • 1: If bit y of FMOD field is set to ‘1’ and if the fault input y is not at the level defined by the bit y of FPOL field, the fault y is cleared and becomes inactive (FMOD and FPOL fields belong to PWM Fault Mode Register), else writing this bit t...

        1076
    • 40.7.27 PWM Fault Protection Value Register 1

      1077
    • 40.7.28 PWM Fault Protection Enable Register

      1078
      • 0: Fault y is not used for the fault protection of channel x.

        1078
      • 1: Fault y is used for the fault protection of channel x.

        1078
    • 40.7.29 PWM Event Line x Register

      1079
    • 40.7.30 PWM Spread Spectrum Register

      1080
    • 40.7.31 PWM Spread Spectrum Update Register

      1081
    • 40.7.32 PWM Stepper Motor Mode Register

      1082
    • 40.7.33 PWM Fault Protection Value Register 2

      1083
    • 40.7.34 PWM Write Protection Control Register

      1084
    • 40.7.35 PWM Write Protection Status Register

      1085
    • 40.7.36 PWM Comparison x Value Register

      1086
    • 40.7.37 PWM Comparison x Value Update Register

      1087
    • 40.7.38 PWM Comparison x Mode Register

      1088
    • 40.7.39 PWM Comparison x Mode Update Register

      1089
    • 40.7.40 PWM Channel Mode Register

      1090
    • 40.7.41 PWM Channel Duty Cycle Register

      1092
    • 40.7.42 PWM Channel Duty Cycle Update Register

      1093
    • 40.7.43 PWM Channel Period Register

      1094
    • 40.7.44 PWM Channel Period Update Register

      1095
    • 40.7.45 PWM Channel Counter Register

      1096
    • 40.7.46 PWM Channel Dead Time Register

      1097
    • 40.7.47 PWM Channel Dead Time Update Register

      1098
    • 40.7.48 PWM Channel Mode Update Register

      1099
    • 40.7.49 PWM Channel Additional Edge Register

      1100
    • 40.7.50 PWM Channel Additional Edge Update Register

      1101
• 41. High Speed MultiMedia Card Interface (HSMCI)

  1102
  • 41.1 Description

    1102
  • 41.2 Embedded Characteristics

    1102
  • 41.3 Block Diagram

    1103
  • 41.4 Application Block Diagram

    1104
  • 41.5 Pin Name List

    1104
  • 41.6 Product Dependencies

    1105
    • 41.6.1 I/O Lines

      1105
    • 41.6.2 Power Management

      1105
    • 41.6.3 Interrupt

      1105
  • 41.7 Bus Topology

    1105
  • 41.8 High Speed MultiMedia Card Operations

    1107
    • 41.8.1 Command - Response Operation

      1108
    • 41.8.2 Data Transfer Operation

      1111
    • 41.8.3 Read Operation

      1111
    • 41.8.4 Write Operation

      1113
  • 41.9 SD/SDIO Card Operation

    1116
    • 41.9.1 SDIO Data Transfer Type

      1116
    • 41.9.2 SDIO Interrupts

      1116
  • 41.10 CE-ATA Operation

    1116
    • 41.10.1 Executing an ATA Polling Command

      1117
    • 41.10.2 Executing an ATA Interrupt Command

      1117
    • 41.10.3 Aborting an ATA Command

      1117
    • 41.10.4 CE-ATA Error Recovery

      1117
  • 41.11 HSMCI Boot Operation Mode

    1118
    • 41.11.1 Boot Procedure, Processor Mode

      1118
  • 41.12 HSMCI Transfer Done Timings

    1118
    • 41.12.1 Definition

      1118
    • 41.12.2 Read Access

      1118
    • 41.12.3 Write Access

      1119
  • 41.13 Register Write Protection

    1120
  • 41.14 High Speed MultiMedia Card Interface (HSMCI) User Interface

    1121
    • 41.14.1 HSMCI Control Register

      1122
    • 41.14.2 HSMCI Mode Register

      1123
    • 41.14.3 HSMCI Data Timeout Register

      1125
    • 41.14.4 HSMCI SDCard/SDIO Register

      1126
    • 41.14.5 HSMCI Argument Register

      1127
    • 41.14.6 HSMCI Command Register

      1128
    • 41.14.7 HSMCI Block Register

      1130
    • 41.14.8 HSMCI Completion Signal Timeout Register

      1131
    • 41.14.9 HSMCI Response Register

      1132
    • 41.14.10 HSMCI Receive Data Register

      1133
    • 41.14.11 HSMCI Transmit Data Register

      1134
    • 41.14.12 HSMCI Status Register

      1135
    • 41.14.13 HSMCI Interrupt Enable Register

      1139
    • 41.14.14 HSMCI Interrupt Disable Register

      1141
    • 41.14.15 HSMCI Interrupt Mask Register

      1143
    • 41.14.16 HSMCI Configuration Register

      1145
    • 41.14.17 HSMCI Write Protection Mode Register

      1146
    • 41.14.18 HSMCI Write Protection Status Register

      1147
• 42. USB Device Port (UDP)

  1148
  • 42.1 Description

    1148
  • 42.2 Embedded Characteristics

    1148
  • 42.3 Block Diagram

    1149
    • 42.3.1 Signal Description

      1149
  • 42.4 Product Dependencies

    1149
    • 42.4.1 I/O Lines

      1150
    • 42.4.2 Power Management

      1150
    • 42.4.3 Interrupt

      1150
  • 42.5 Typical Connection

    1151
    • 42.5.1 USB Device Transceiver

      1151
    • 42.5.2 VBUS Monitoring

      1151
  • 42.6 Functional Description

    1152
    • 42.6.1 USB 2.0 Full-speed Introduction

      1152
      • 42.6.1.1 USB 2.0 Full-speed Transfer Types

        1152
      • 42.6.1.2 USB Bus Transactions

        1152
      • 42.6.1.3 USB Transfer Event Definitions

        1153
    • 42.6.2 Handling Transactions with USB 2.0 Device Peripheral

      1154
      • 42.6.2.1 Setup Transaction

        1154
      • 42.6.2.2 Data IN Transaction

        1154
        • Using Endpoints Without Ping-pong Attributes

          1154
        • Using Endpoints With Ping-pong Attribute

          1155
      • 42.6.2.3 Data OUT Transaction

        1157
        • Data OUT Transaction Without Ping-pong Attributes

          1157
        • Using Endpoints With Ping-pong Attributes

          1158
      • 42.6.2.4 Stall Handshake

        1160
      • 42.6.2.5 Transmit Data Cancellation

        1161
        • Endpoints Without Dual-Banks

          1161
        • Endpoints With Dual-Banks

          1161
    • 42.6.3 Controlling Device States

      1162
      • 42.6.3.1 Not Powered State

        1162
      • 42.6.3.2 Entering Attached State

        1163
      • 42.6.3.3 From Powered State to Default State

        1163
      • 42.6.3.4 From Default State to Address State

        1163
      • 42.6.3.5 From Address State to Configured State

        1163
      • 42.6.3.6 Entering in Suspend State

        1163
      • 42.6.3.7 Receiving a Host Resume

        1164
      • 42.6.3.8 Sending a Device Remote Wakeup

        1164
  • 42.7 USB Device Port (UDP) User Interface

    1165
    • 42.7.1 UDP Frame Number Register

      1166
    • 42.7.2 UDP Global State Register

      1167
    • 42.7.3 UDP Function Address Register

      1169
    • 42.7.4 UDP Interrupt Enable Register

      1170
    • 42.7.5 UDP Interrupt Disable Register

      1172
    • 42.7.6 UDP Interrupt Mask Register

      1174
    • 42.7.7 UDP Interrupt Status Register

      1176
    • 42.7.8 UDP Interrupt Clear Register

      1178
    • 42.7.9 UDP Reset Endpoint Register

      1179
    • 42.7.10 UDP Endpoint Control and Status Register (CONTROL_BULK)

      1180
    • 42.7.11 UDP Endpoint Control and Status Register (ISOCHRONOUS)

      1185
    • 42.7.12 UDP FIFO Data Register

      1189
    • 42.7.13 UDP Transceiver Control Register

      1190
• 43. Ethernet MAC (GMAC)

  1191
  • 43.1 Description

    1191
  • 43.2 Embedded Characteristics

    1191
  • 43.3 Block Diagram

    1192
  • 43.4 Signal Interface

    1193
  • 43.5 Functional Description

    1193
    • 43.5.1 Media Access Controller

      1193
    • 43.5.2 1588 Time Stamp Unit

      1194
    • 43.5.3 AHB Direct Memory Access Interface

      1194
      • 43.5.3.1 Receive AHB Buffers

        1194
      • 43.5.3.2 Transmit AHB Buffers

        1197
      • 43.5.3.3 DMA Bursting on the AHB

        1199
    • 43.5.4 MAC Transmit Block

      1199
    • 43.5.5 MAC Receive Block

      1200
    • 43.5.6 Checksum Offload for IP, TCP and UDP

      1201
      • 43.5.6.1 Receiver Checksum Offload

        1201
    • 43.5.7 MAC Filtering Block

      1201
    • 43.5.8 Broadcast Address

      1203
    • 43.5.9 Hash Addressing

      1203
    • 43.5.10 Copy all Frames (Promiscuous Mode)

      1203
    • 43.5.11 Disable Copy of Pause Frames

      1203
    • 43.5.12 VLAN Support

      1204
    • 43.5.13 IEEE 1588 Support

      1204
    • 43.5.14 Time Stamp Unit

      1208
    • 43.5.15 MAC 802.3 Pause Frame Support

      1209
      • 43.5.15.1 802.3 Pause Frame Reception

        1209
      • 43.5.15.2 802.3 Pause Frame Transmission

        1210
    • 43.5.16 MAC PFC Priority-based Pause Frame Support

      1211
      • 43.5.16.1 PFC Pause Frame Reception

        1211
      • 43.5.16.2 PFC Pause Frame Transmission

        1211
    • 43.5.17 PHY Interface

      1212
    • 43.5.18 10/100 Operation

      1212
    • 43.5.19 Jumbo Frames

      1212
  • 43.6 Programming Interface

    1213
    • 43.6.1 Initialization

      1213
      • 43.6.1.1 Configuration

        1213
      • 43.6.1.2 Receive Buffer List

        1213
      • 43.6.1.3 Transmit Buffer List

        1214
      • 43.6.1.4 Address Matching

        1214
      • 43.6.1.5 PHY Maintenance

        1214
      • 43.6.1.6 Interrupts

        1214
      • 43.6.1.7 Transmitting Frames

        1215
      • 43.6.1.8 Receiving Frames

        1215
    • 43.6.2 Statistics Registers

      1215
  • 43.7 Ethernet MAC (GMAC) User Interface

    1217
    • 43.7.1 Network Control Register

      1220
    • 43.7.2 Network Configuration Register

      1222
    • 43.7.3 Network Status Register

      1225
    • 43.7.4 User Register

      1226
    • 43.7.5 DMA Configuration Register

      1227
    • 43.7.6 Transmit Status Register

      1229
    • 43.7.7 Receive Buffer Queue Base Address Register

      1231
    • 43.7.8 Transmit Buffer Queue Base Address Register

      1232
    • 43.7.9 Receive Status Register

      1233
    • 43.7.10 Interrupt Status Register

      1234
    • 43.7.11 Interrupt Enable Register

      1236
    • 43.7.12 Interrupt Disable Register

      1238
    • 43.7.13 Interrupt Mask Register

      1240
    • 43.7.14 PHY Maintenance Register

      1245
    • 43.7.15 Receive Pause Quantum Register

      1247
    • 43.7.16 Transmit Pause Quantum Register

      1248
    • 43.7.17 Hash Register Bottom [31:0]

      1249
    • 43.7.18 Hash Register Top [63:32]

      1250
    • 43.7.19 Specific Address 1 Bottom [31:0] Register

      1251
    • 43.7.20 Specific Address 1 Top [47:32] Register

      1252
    • 43.7.21 Specific Address 2 Bottom [31:0] Register

      1253
    • 43.7.22 Specific Address 2 Top [47:32] Register

      1254
    • 43.7.23 Specific Address 3 Bottom [31:0] Register

      1255
    • 43.7.24 Specific Address 3 Top [47:32] Register

      1256
    • 43.7.25 Specific Address 4 Bottom Register[31:0]

      1257
    • 43.7.26 Specific Address 4 Top Register[47:32]

      1258
    • 43.7.27 Type ID Match 1 Register

      1259
    • 43.7.28 Type ID Match 2 Register

      1260
    • 43.7.29 Type ID Match 3 Register

      1261
    • 43.7.30 Type ID Match 4 Register

      1262
    • 43.7.31 IPG Stretch Register

      1263
    • 43.7.32 Stacked VLAN Register

      1264
    • 43.7.33 Transmit PFC Pause Register

      1265
    • 43.7.34 Specific Address 1 Mask Bottom [31:0] Register

      1266
    • 43.7.35 Specific Address Mask 1 Top [47:32] Register

      1267
    • 43.7.36 Octets Transmitted [31:0] Register

      1268
    • 43.7.37 Octets Transmitted [47:32] Register

      1269
    • 43.7.38 Frames Transmitted Register

      1270
    • 43.7.39 Broadcast Frames Transmitted Register

      1271
    • 43.7.40 Multicast Frames Transmitted Register

      1272
    • 43.7.41 Pause Frames Transmitted Register

      1273
    • 43.7.42 64 Byte Frames Transmitted Register

      1274
    • 43.7.43 65 to 127 Byte Frames Transmitted Register

      1275
    • 43.7.44 128 to 255 Byte Frames Transmitted Register

      1276
    • 43.7.45 256 to 511 Byte Frames Transmitted Register

      1277
    • 43.7.46 512 to 1023 Byte Frames Transmitted Register

      1278
    • 43.7.47 1024 to 1518 Byte Frames Transmitted Register

      1279
    • 43.7.48 Greater Than 1518 Byte Frames Transmitted Register

      1280
    • 43.7.49 Transmit Underruns Register

      1281
    • 43.7.50 Single Collision Frames Register

      1282
    • 43.7.51 Multiple Collision Frames Register

      1283
    • 43.7.52 Excessive Collisions Register

      1284
    • 43.7.53 Late Collisions Register

      1285
    • 43.7.54 Deferred Transmission Frames Register

      1286
    • 43.7.55 Carrier Sense Errors Register

      1287
    • 43.7.56 Octets Received [31:0] Register

      1288
    • 43.7.57 Octets Received [47:32] Register

      1289
    • 43.7.58 Frames Received Register

      1290
    • 43.7.59 Broadcast Frames Received Register

      1291
    • 43.7.60 Multicast Frames Received Register

      1292
    • 43.7.61 Pause Frames Received Register

      1293
    • 43.7.62 64 Byte Frames Received Register

      1294
    • 43.7.63 65 to 127 Byte Frames Received Register

      1295
    • 43.7.64 128 to 255 Byte Frames Received Register

      1296
    • 43.7.65 256 to 511 Byte Frames Received Register

      1297
    • 43.7.66 512 to 1023 Byte Frames Received Register

      1298
    • 43.7.67 1024 to 1518 Byte Frames Received Register

      1299
    • 43.7.68 1519 to Maximum Byte Frames Received Register

      1300
    • 43.7.69 Undersized Frames Received Register

      1301
    • 43.7.70 Oversized Frames Received Register

      1302
    • 43.7.71 Jabbers Received Register

      1303
    • 43.7.72 Frame Check Sequence Errors Register

      1304
    • 43.7.73 Length Field Frame Errors Register

      1305
    • 43.7.74 Receive Symbol Errors Register

      1306
    • 43.7.75 Alignment Errors Register

      1307
    • 43.7.76 Receive Resource Errors Register

      1308
    • 43.7.77 Receive Overruns Register

      1309
    • 43.7.78 IP Header Checksum Errors Register

      1310
    • 43.7.79 TCP Checksum Errors Register

      1311
    • 43.7.80 UDP Checksum Errors Register

      1312
    • 43.7.81 1588 Timer Sync Strobe Seconds [31:0] Register

      1313
    • 43.7.82 1588 Timer Sync Strobe Nanoseconds Register

      1314
    • 43.7.83 1588 Timer Seconds [31:0] Register

      1315
    • 43.7.84 1588 Timer Nanoseconds Register

      1316
    • 43.7.85 1588 Timer Adjust Register

      1317
    • 43.7.86 1588 Timer Increment Register

      1318
    • 43.7.87 PTP Event Frame Transmitted Seconds Register

      1319
    • 43.7.88 PTP Event Frame Transmitted Nanoseconds Register

      1320
    • 43.7.89 PTP Event Frame Received Seconds Register

      1321
    • 43.7.90 PTP Event Frame Received Nanoseconds Register

      1322
    • 43.7.91 PTP Peer Event Frame Transmitted Seconds Register

      1323
    • 43.7.92 PTP Peer Event Frame Transmitted Nanoseconds Register

      1324
    • 43.7.93 PTP Peer Event Frame Received Seconds Register

      1325
• 44. Analog Comparator Controller (ACC)

  1326
  • 44.1 Description

    1326
  • 44.2 Embedded Characteristics

    1326
  • 44.3 Block Diagram

    1327
  • 44.4 Pin Name List

    1328
  • 44.5 Product Dependencies

    1328
    • 44.5.1 I/O Lines

      1328
    • 44.5.2 Power Management

      1328
    • 44.5.3 Interrupt

      1328
    • 44.5.4 Fault Output

      1328
  • 44.6 Functional Description

    1329
    • 44.6.1 Description

      1329
    • 44.6.2 Analog Settings

      1329
    • 44.6.3 Output Masking Period

      1329
    • 44.6.4 Fault Mode

      1329
    • 44.6.5 Register Write Protection

      1329
  • 44.7 Analog Comparator Controller (ACC) User Interface

    1330
    • 44.7.1 ACC Control Register

      1331
    • 44.7.2 ACC Mode Register

      1332
    • 44.7.3 ACC Interrupt Enable Register

      1334
    • 44.7.4 ACC Interrupt Disable Register

      1335
    • 44.7.5 ACC Interrupt Mask Register

      1336
    • 44.7.6 ACC Interrupt Status Register

      1337
    • 44.7.7 ACC Analog Control Register

      1338
    • 44.7.8 ACC Write Protection Mode Register

      1339
    • 44.7.9 ACC Write Protection Status Register

      1340
• 45. Analog-Front-End Controller (AFEC)

  1341
  • 45.1 Description

    1341
  • 45.2 Embedded Characteristics

    1341
  • 45.3 Block Diagram

    1342
  • 45.4 Signal Description

    1342
  • 45.5 Product Dependencies

    1343
    • 45.5.1 Power Management

      1343
    • 45.5.2 Interrupt Sources

      1343
    • 45.5.3 Analog Inputs

      1343
    • 45.5.4 Temperature Sensor

      1343
    • 45.5.5 I/O Lines

      1343
    • 45.5.6 Timer Triggers

      1344
    • 45.5.7 PWM Event Line

      1344
    • 45.5.8 Fault Output

      1344
    • 45.5.9 Conversion Performances

      1344
  • 45.6 Functional Description

    1344
    • 45.6.1 Analog-Front-End Conversion

      1344
    • 45.6.2 Conversion Reference

      1345
    • 45.6.3 Conversion Resolution

      1346
      • 45.6.3.1 Enhanced Resolution Mode

        1346
    • 45.6.4 Conversion Results

      1346
    • 45.6.5 Conversion Results Format

      1349
    • 45.6.6 Conversion Triggers

      1349
    • 45.6.7 Sleep Mode and Conversion Sequencer

      1349
    • 45.6.8 Comparison Window

      1350
    • 45.6.9 Differential Inputs

      1350
    • 45.6.10 Input Gain and Offset

      1351
    • 45.6.11 AFEC Timings

      1352
    • 45.6.12 Temperature Sensor

      1353
    • 45.6.13 Enhanced Resolution Mode and Digital Averaging Function

      1356
    • 45.6.14 Automatic Calibration

      1359
    • 45.6.15 Buffer Structure

      1360
    • 45.6.16 Fault Output

      1360
    • 45.6.17 Register Write Protection

      1360
  • 45.7 Analog-Front-End Controller (AFEC) User Interface

    1361
    • 45.7.1 AFEC Control Register

      1363
    • 45.7.2 AFEC Mode Register

      1364
    • 45.7.3 AFEC Extended Mode Register

      1367
    • 45.7.4 AFEC Channel Sequence 1 Register

      1369
    • 45.7.5 AFEC Channel Sequence 2 Register

      1370
    • 45.7.6 AFEC Channel Enable Register

      1371
    • 45.7.7 AFEC Channel Disable Register

      1372
    • 45.7.8 AFEC Channel Status Register

      1373
    • 45.7.9 AFEC Last Converted Data Register

      1374
    • 45.7.10 AFEC Interrupt Enable Register

      1375
    • 45.7.11 AFEC Interrupt Disable Register

      1376
    • 45.7.12 AFEC Interrupt Mask Register

      1377
    • 45.7.13 AFEC Interrupt Status Register

      1378
    • 45.7.14 AFEC Overrun Status Register

      1380
    • 45.7.15 AFEC Compare Window Register

      1381
    • 45.7.16 AFEC Channel Gain Register

      1382
    • 45.7.17 AFEC Channel Calibration DC Offset Register

      1383
    • 45.7.18 AFEC Channel Differential Register

      1384
    • 45.7.19 AFEC Channel Selection Register

      1385
    • 45.7.20 AFEC Channel Data Register

      1386
    • 45.7.21 AFEC Channel Offset Compensation Register

      1387
    • 45.7.22 AFEC Temperature Sensor Mode Register

      1388
    • 45.7.23 AFEC Temperature Compare Window Register

      1389
    • 45.7.24 AFEC Analog Control Register

      1390
    • 45.7.25 AFEC Write Protection Mode Register

      1391
    • 45.7.26 AFEC Write Protection Status Register

      1392
• 46. Digital-to-Analog Converter Controller (DACC)

  1393
  • 46.1 Description

    1393
  • 46.2 Embedded Characteristics

    1393
  • 46.3 Block Diagram

    1394
  • 46.4 Signal Description

    1395
  • 46.5 Product Dependencies

    1395
    • 46.5.1 Power Management

      1395
    • 46.5.2 Interrupt Sources

      1395
    • 46.5.3 Conversion Performances

      1395
  • 46.6 Functional Description

    1396
    • 46.6.1 Digital-to-Analog Conversion

      1396
    • 46.6.2 Conversion Results

      1396
    • 46.6.3 Conversion Triggers

      1396
    • 46.6.4 Conversion FIFO

      1396
    • 46.6.5 Channel Selection

      1396
    • 46.6.6 DACC Timings

      1397
    • 46.6.7 Register Write Protection

      1397
  • 46.7 Digital-to-Analog Converter Controller (DACC) User Interface

    1398
    • 46.7.1 DACC Control Register

      1399
    • 46.7.2 DACC Mode Register

      1400
    • 46.7.3 DACC Channel Enable Register

      1404
    • 46.7.4 DACC Channel Disable Register

      1405
    • 46.7.5 DACC Channel Status Register

      1406
    • 46.7.6 DACC Conversion Data Register

      1407
    • 46.7.7 DACC Interrupt Enable Register

      1408
    • 46.7.8 DACC Interrupt Disable Register

      1409
    • 46.7.9 DACC Interrupt Mask Register

      1410
    • 46.7.10 DACC Interrupt Status Register

      1411
    • 46.7.11 DACC Analog Current Register

      1412
    • 46.7.12 DACC Write Protection Mode Register

      1413
    • 46.7.13 DACC Write Protection Status Register

      1414
• 47. SAM4E Electrical Characteristics

  1415
  • 47.1 Absolute Maximum Ratings

    1415
  • 47.2 DC Characteristics

    1416
  • 47.3 Power Consumption

    1422
    • 47.3.1 Backup Mode Current Consumption

      1422
      • 47.3.1.1 Configuration A: Embedded Slow Clock RC Oscillator Enabled

        1422
      • 47.3.1.2 Configuration B: 32.768 kHz Crystal Oscillator Enabled

        1422
    • 47.3.2 Sleep and Wait Mode Current Consumption

      1423
      • 47.3.2.1 Sleep Mode

        1423
      • 47.3.2.2 Wait Mode

        1425
    • 47.3.3 Active Mode Power Consumption

      1426
      • 47.3.3.1 SAM4E Active Power Consumption

        1427
      • 47.3.3.2 SAM4E Active Total Power Consumption

        1428
    • 47.3.4 Peripheral Power Consumption in Active Mode

      1429
  • 47.4 Oscillator Characteristics

    1430
    • 47.4.1 32 kHz RC Oscillator Characteristics

      1430
    • 47.4.2 4/8/12 MHz RC Oscillators Characteristics

      1430
    • 47.4.3 32.768 kHz Crystal Oscillator Characteristics

      1431
    • 47.4.4 32.768 kHz Crystal Characteristics

      1432
    • 47.4.5 3 to 20 MHz Crystal Oscillator Characteristics

      1432
    • 47.4.6 3 to 20 MHz Crystal Characteristics

      1433
    • 47.4.7 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode

      1433
    • 47.4.8 Crystal Oscillator Design Considerations Information

      1434
      • 47.4.8.1 Choosing a Crystal

        1434
      • 47.4.8.2 Printed Circuit Board (PCB)

        1434
  • 47.5 PLLA Characteristics

    1434
  • 47.6 USB Transceiver Characteristics

    1435
    • 47.6.1 Typical Connection

      1435
    • 47.6.2 Electrical Characteristics

      1435
    • 47.6.3 Switching Characteristics

      1436
  • 47.7 12-bit AFE (Analog Front End) Characteristics

    1437
    • 47.7.1 ADC Power Supply

      1437
      • 47.7.1.1 ADC Bias Current

        1437
    • 47.7.2 External Reference Voltage

      1438
    • 47.7.3 ADC Timings

      1438
    • 47.7.4 ADC Transfer Function

      1439
      • 47.7.4.1 Differential Mode

        1439
      • 47.7.4.2 Single-ended Mode

        1439
      • 47.7.4.3 Example of LSB Computation

        1440
    • 47.7.5 ADC Electrical Characteristics

      1440
      • 47.7.5.1 Gain and Offset Errors

        1440
        • Differential Mode

          1441
        • Single-ended Mode

          1442
      • 47.7.5.2 ADC Electrical Performances

        1443
        • Single-ended Static Performances

          1443
        • Single-ended Dynamic Performances

          1443
        • Differential Static Performances

          1443
        • Differential Dynamic Performances

          1443
        • 10-bit ADC Mode

          1443
        • Low Voltage Supply

          1444
      • 47.7.5.3 ADC Channel Input Impedance

        1444
        • Track and Hold Time versus Source Output Impedance

          1445
      • 47.7.5.4 AFE DAC Offset Compensation

        1445
    • 47.7.6 ADC Resolution with Averaging

      1447
      • 47.7.6.1 Conditions @ 25°C with Gain =1

        1447
      • 47.7.6.2 Conditions @ 25°C with Gain =4

        1448
  • 47.8 12-bit DAC Characteristics

    1449
  • 47.9 Analog Comparator Characteristics

    1451
  • 47.10 Temperature Sensor

    1451
  • 47.11 AC Characteristics

    1452
    • 47.11.1 Master Clock Characteristics

      1452
    • 47.11.2 I/O Characteristics

      1452
    • 47.11.3 SPI Characteristics

      1453
      • 47.11.3.1 Maximum SPI Frequency

        1454
      • 47.11.3.2 SPI Timings

        1455
    • 47.11.4 HSMCI Timings

      1456
    • 47.11.5 SMC Timings

      1456
      • 47.11.5.1 Read Timings

        1456
      • 47.11.5.2 Write Timings

        1458
    • 47.11.6 USART in SPI Mode Timings

      1460
      • 47.11.6.1 USART SPI TImings

        1462
    • 47.11.7 Two-wire Serial Interface Characteristics

      1463
    • 47.11.8 Ethernet MAC (GMAC) Characteristics

      1464
      • 47.11.8.1 Timing Conditions

        1464
      • 47.11.8.2 Timing Constraints

        1464
      • 47.11.8.3 MII Mode

        1465
    • 47.11.9 Embedded Flash Characteristics

      1467
• 48. SAM4E Mechanical Characteristics

  1469
  • 48.1 100-ball TFBGA Package Drawing

    1469
  • 48.2 144-ball LFBGA Package Drawing

    1470
  • 48.3 100-lead LQFP Package Drawing

    1471
  • 48.4 144-lead LQFP Package Drawing

    1472
  • 48.5 Soldering Profile

    1473
  • 48.6 Packaging Resources

    1473
• 49. Marking

  1474
• 50. Ordering Information

  1475
• 51. Errata on SAM4E Devices

  1476
  • 51.1 Errata

    1476
    • 51.1.1 Watchdog

      1476
      • 51.1.1.1 Watchdog Not Stopped in Wait Mode

        1476
    • 51.1.2 Brownout Detector

      1476
      • 51.1.2.1 Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected

        1476
    • 51.1.3 Flash

      1477
      • 51.1.3.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State

        1477
• 52. Revision History

  1478
• Table of Contents

  1498