Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet

1211

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

Note:

Refer to the 802.1Qbb standard for a full description of priority-based pause operation.

The following table shows the start of a Priority-based Flow Control (PFC) pause frame.

The GMAC supports PFC priority-based pause transmission and reception. Before PFC pause frames can be
received, bit 16 of the Network Control Register must be set.

The ability to receive and decode priority-based pause frames is enabled by setting bit 16 of the Network Control
Register. When this bit is set, the GMAC will match either classic 802.3 pause frames or PFC priority-based pause
frames. Once a priority-based pause frame has been received and matched, then from that moment on the GMAC
will only match on priority-based pause frames (this is an 802.1Qbb requirement, known as PFC negotiation).
Once priority-based pause has been negotiated, any received 802.3x format pause frames will not be acted upon.

If a valid priority-based pause frame is received then the GMAC will decode the frame and determine which, if any,
of the eight priorities require to be paused. Up to eight Pause Time Registers are then updated with the eight
pause times extracted from the frame regardless of whether a previous pause operation is active or not. An
interrupt (either bit 12 or bit 13 of the Interrupt Status Register) is triggered when a pause frame is received, but
only if the interrupt has been enabled (bit 12 and bit 13 of the Interrupt Mask Register). Pause frames received with
non zero quantum are indicated through the interrupt bit 12 of the Interrupt Status Register. Pause frames received
with zero quantum are indicated on bit 13 of the Interrupt Status Register. The loading of a new pause time only
occurs when the GMAC is configured for full duplex operation. If the GMAC is configured for half duplex, the pause
time counters will not be loaded, but the pause frame received interrupt will still be triggered. A valid pause frame
is defined as having a destination address that matches either the address stored in Specific Address Register 1 or
if it matches the reserved address of 0x0180C2000001. It must also have the MAC control frame type ID of 0x8808
and have the pause opcode of 0x0101.

Pause frames that have frame check sequence (FCS) or other errors will be treated as invalid and will be
discarded. Valid pause frames received will increment the Pause Frames Received Statistic Register.

The Pause Time Registers decrement every 512 bit times immediately following the PFC frame reception. For test
purposes, the retry test bit can be set (bit 12 in the Network Configuration Register) which causes the Pause Time
Register to decrement every GRXCK cycle once transmission has stopped.

The interrupt (bit 13 in the Interrupt Status Register) is asserted whenever the Pause Time Register decrements to
zero (assuming it has been enabled by bit 13 in the Interrupt Mask Register). This interrupt is also set when a zero
quantum pause frame is received.

Automatic transmission of pause frames is supported through the transmit priority-based pause frame bit of the
Network Control Register. If bit 17 of the Network Control Register is written with logic 1, a PFC pause frame will
be transmitted providing full duplex is selected in the Network Configuration Register and the transmit block is
enabled in the Network Control Register. When bit 17 of the Network Control Register is set, the fields of the
priority-based pause frame will be built using the values stored in the Transmit PFC Pause Register.

Pause frame transmission will happen immediately if transmit is inactive or if transmit is active between the current
frame and the next frame due to be transmitted.

0x0180C2000001

6 bytes

0x8808

0x1001

2 bytes

8 

× 2 bytes