Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

300

Unaligned

A data item stored at an address that is not divisible by the number of bytes that defines the data size 
is said to be unaligned. For example, a word stored at an address that is not divisible by four.

Undefined 

Indicates an instruction that generates an Undefined instruction exception.

Unpredictable

One cannot rely on the behavior. Unpredictable behavior must not represent security holes. 
Unpredictable behavior must not halt or hang the processor, or any parts of the system.

Warm reset

Also known as a core reset. Initializes the majority of the processor excluding the debug controller and 
debug logic. This type of reset is useful if debugging features of a processor.

WA

.

WB

Word

A 32-bit data item.

Write

Writes are defined as operations that have the semantics of a store. Writes include the Thumb 
instructions STM, STR, STRH, STRB, and PUSH.

Write-allocate (WA)

In a write-allocate cache, a cache miss on storing data causes a cache line to be allocated into the 
cache.

Write-back (WB)

In a write-back cache, data is only written to main memory when it is forced out of the cache on line 
replacement following a cache miss. Otherwise, writes by the processor only update the cache. This is 
also known as copyback.

Write buffer

A block of high-speed memory, arranged as a FIFO buffer, between the data cache and main memory, 
whose purpose is to optimize stores to main memory.

Write-through (WT)

In a write-through cache, data is written to main memory at the same time as the cache is updated.