Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet

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SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit) prefetch buffers and
one 128-bit (or 64-bit) data read buffer, thus providing maximum system performance. This buffer is added in order
to store the requested data plus all the data contained in the 128-bit (64-bit) aligned data. This speeds up
sequential data reads if, for example, FWS is equal to 1 (see 

). The data read optimization is enabled

by default. If the SCOD bit in EEFC_FMR is set to 1, this buffer is disabled and the data read is no longer
optimized.

Note:

No consecutive data read accesses are mandatory to benefit from this optimization.

The EEFC offers a set of commands to manage programming the Flash memory, locking and unlocking lock
regions, consecutive programming, locking and full Flash erasing, etc. 

Flash Access

Buffer (128bits)

Master Clock

ARM Request

       (32-bit)

XXX

Data To ARM

Bytes 0-15

Bytes 16-31

Bytes 0-15

Bytes 0-3

4-7

8-11

12-15

16-19

20-23

XXX

Bytes 16-31

@Byte 0

@ 4

@ 8

@ 12

@ 16

@ 20

@ 24

@ 28

@ 32

@ 36

XXX

Bytes 32-47

24-27

28-31

32-35

Get Flash descriptor

0x00

GETD

Write page

0x01

WP

Write page and lock

0x02

WPL

Erase page and write page

0x03

EWP

Erase page and write page then lock

0x04

EWPL

Erase all

0x05

EA

Erase pages

0x07

EPA

Set lock bit

0x08

SLB

Clear lock bit

0x09

CLB

Get lock bit

0x0A

GLB

Set GPNVM bit

0x0B

SGPB

Clear GPNVM bit

0x0C

CGPB

Get GPNVM bit

0x0D

GGPB