Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet
Product codes
ATSAM4E-EK
583
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
29.6
Divider and PLL Block
The device features one divider/one PLL block that permits a wide range of frequencies to be selected on either
the master clock, the processor clock or the programmable clock outputs. Additionally, they provide a 48 MHz
signal to the embedded USB device port regardless of the frequency of the main clock.
the master clock, the processor clock or the programmable clock outputs. Additionally, they provide a 48 MHz
signal to the embedded USB device port regardless of the frequency of the main clock.
shows the block diagram of the dividers and PLL blocks.
Figure 29-4.
Divider and PLL Block Diagram
Divider
DIVA
PLLA
MULA
PLLACOUNT
LOCKA
SLCK
MAINCK
PLLACK
PLLA
Counter
CKGR_PLLAR
CKGR_PLLAR
CKGR_PLLAR
PMC_SR