Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet
Product codes
ATSAM4E-EK
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
590
30.12 Startup from Embedded Flash
The inherent start-up time of the embedded Flash cannot provide a fast startup of the system.
If system fast start-up time is not required, the first instruction after a wait mode exit can be located in the
embedded Flash. Under these conditions, prior to entering wait mode, the Flash controller must be programmed to
perform access in 0 wait-state (see Flash controller section).
embedded Flash. Under these conditions, prior to entering wait mode, the Flash controller must be programmed to
perform access in 0 wait-state (see Flash controller section).
The procedure and conditions to enter wait mode and the circuitry to exit wait mode are strictly the same as fast
startup (see
startup (see
).
30.13 Main Clock Failure Detector
The clock failure detector monitors the main crystal oscillator or ceramic resonator-based oscillator to identify an
eventual failure of this oscillator.
eventual failure of this oscillator.
The clock failure detector can be enabled or disabled by bit CFDEN in CKGR_MOR. After a VDDCORE reset, the
detector is disabled. However, if the oscillator is disabled (MOSCXTEN = 0), the detector is disabled too.
detector is disabled. However, if the oscillator is disabled (MOSCXTEN = 0), the detector is disabled too.
The clock failure detection must be enabled only when system clock MCK selects the fast RC oscillator. PMC_SR
must be read two slow clock cycles after enabling the clock failure detector. Then, MCK can select another clock
source by programming the CSS field in PMC_MCKR.
must be read two slow clock cycles after enabling the clock failure detector. Then, MCK can select another clock
source by programming the CSS field in PMC_MCKR.
A failure is detected by means of a counter incrementing on the main oscillator clock edge and timing logic clocked
on the slow RC oscillator controlling the counter. Thus, the slow RC oscillator must be enabled.
on the slow RC oscillator controlling the counter. Thus, the slow RC oscillator must be enabled.
The counter is cleared when the slow RC oscillator clock signal is low and enabled when the signal is high. Thus
the failure detection time is 1 slow RC oscillator clock period. If, during the high level period of the slow RC
oscillator clock signal, less than 8 fast crystal oscillator clock periods have been counted, then a failure is reported.
the failure detection time is 1 slow RC oscillator clock period. If, during the high level period of the slow RC
oscillator clock signal, less than 8 fast crystal oscillator clock periods have been counted, then a failure is reported.
If a failure of the main oscillator is detected, bit CFDEV in PMC_SR indicates a failure event and generates an
interrupt if the corresponding interrupt source is enabled. The interrupt remains active until a read occurs in
PMC_SR. The user can know the status of the clock failure detection at any time by reading the CFDS bit in
PMC_SR.
interrupt if the corresponding interrupt source is enabled. The interrupt remains active until a read occurs in
PMC_SR. The user can know the status of the clock failure detection at any time by reading the CFDS bit in
PMC_SR.
Figure 30-5.
Clock Failure Detection (Example)
If the main oscillator is selected as the source clock of MAINCK (MOSCSEL in CKGR_MOR = 1), and if the master
clock source is PLLACK (CSS = 2), a clock failure detection automatically forces MAINCK to be the source clock
for the master clock (MCK).Then, regardless of the PMC configuration, a clock failure detection automatically
forces the fast RC oscillator to be the source clock for MAINCK. If the fast RC oscillator is disabled when a clock
failure detection occurs, it is automatically re-enabled by the clock failure detection mechanism.
clock source is PLLACK (CSS = 2), a clock failure detection automatically forces MAINCK to be the source clock
for the master clock (MCK).Then, regardless of the PMC configuration, a clock failure detection automatically
forces the fast RC oscillator to be the source clock for MAINCK. If the fast RC oscillator is disabled when a clock
failure detection occurs, it is automatically re-enabled by the clock failure detection mechanism.
Main Crytal Clock
SLCK
Note: ratio of clock periods is for illustration purposes only
CDFEV
CDFS
Read PMC_SR