Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet
Product codes
ATSAM4E-EK
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
794
Figure 35-4.
SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
35.7.3 Master Mode Operations
When configured in Master mode, the SPI operates on the clock generated by the internal programmable baud
rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives
the chip select line to the slave and the serial clock signal (SPCK).
rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives
the chip select line to the slave and the serial clock signal (SPCK).
The SPI features two holding registers, the Transmit Data register (SPI_TDR) and the Receive Data register
(SPI_RDR), and a single shift register. The holding registers maintain the data flow at a constant rate.
(SPI_RDR), and a single shift register. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a data transfer starts when the processor writes to the SPI_TDR. The written data is
immediately transferred in the Shift register and the transfer on the SPI bus starts. While the data in the Shift
register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift register. Data cannot be
loaded in the SPI_RDR without transmitting data. If there is no data to transmit, a dummy data can be used
(SPI_TDR filled with ones). When the WDRBT bit is set, a new data cannot be transmitted if the SPI_RDR has not
been read. If Receiving mode is not required, for example when communicating with a slave receiver only (such as
an LCD), the receive status flags in the SPI Status register (SPI_SR) can be discarded.
immediately transferred in the Shift register and the transfer on the SPI bus starts. While the data in the Shift
register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift register. Data cannot be
loaded in the SPI_RDR without transmitting data. If there is no data to transmit, a dummy data can be used
(SPI_TDR filled with ones). When the WDRBT bit is set, a new data cannot be transmitted if the SPI_RDR has not
been read. If Receiving mode is not required, for example when communicating with a slave receiver only (such as
an LCD), the receive status flags in the SPI Status register (SPI_SR) can be discarded.
Before writing the TDR, the PCS field in the SPI_MR must be set in order to select a slave.
If new data is written in the SPI_TDR during the transfer, it is kept in the SPI_TDR until the current transfer is
completed. Then, the received data is transferred from the Shift register to the SPI_RDR, the data in the SPI_TDR
is loaded in the Shift register and a new transfer starts.
completed. Then, the received data is transferred from the Shift register to the SPI_RDR, the data in the SPI_TDR
is loaded in the Shift register and a new transfer starts.
The transfer of a data written in the SPI_TDR to the Shift register is indicated by the Transmit Data Register Empty
(TDRE) bit in the SPI_SR. When new data is written in the SPI_TDR, this bit is cleared. The TDRE bit is used to
trigger the Transmit PDC or DMA channel.
(TDRE) bit in the SPI_SR. When new data is written in the SPI_TDR, this bit is cleared. The TDRE bit is used to
trigger the Transmit PDC or DMA channel.
The end of transfer is indicated by the TXEMPTY flag in the SPI_SR. If a transfer delay (DLYBCT) is greater than
0 for the last transfer, TXEMPTY is set after the completion of this delay. The peripheral clock can be switched off
at this time.
0 for the last transfer, TXEMPTY is set after the completion of this delay. The peripheral clock can be switched off
at this time.
The transfer of received data from the Shift register to the SPI_RDR is indicated by the Receive Data Register Full
(RDRF) bit in the SPI_SR. When the received data is read, the RDRF bit is cleared.
(RDRF) bit in the SPI_SR. When the received data is read, the RDRF bit is cleared.
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
1
2
3
4
5
7
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference)
8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
* Not defined.
2
2
6
*