Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet

Product codes

ATSAM4E-EK

869

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

Figure 37-4.

Character Reception

37.5.2.3 Receiver Ready

When a complete character is received, it is transferred to the Receive Holding Register (UART_RHR) and the
RXRDY status bit in the Status Register (UART_SR) is set. The bit RXRDY is automatically cleared when
UART_RHR is read.

Figure 37-5.

Receiver Ready

37.5.2.4 Receiver Overrun

The OVRE status bit in UART_SR is set if UART_RHR has not been read by the software (or the Peripheral Data
Controller or DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received.
OVRE is cleared when the software writes a 1 to the bit RSTSTA (Reset Status) in UART_CR.

Figure 37-6.

Receiver Overrun

37.5.2.5 Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with
the field PAR in the Mode Register (UART_MR). It then compares the result with the received parity bit. If different,
the parity error bit PARE in UART_SR is set at the same time RXRDY is set. The parity bit is cleared when
UART_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status
command is written, the PARE bit remains at 1.

URXD

True Start Detection

Sampling

Parity Bit

Stop Bit

Example: 8-bit, parity enabled 1 stop

1 bit

period

0.5 bit
period

URXD

Read UART_RHR

RXRDY

URXD

RSTSTA

RXRDY

OVRE

stop