Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet
Product codes
ATSAM4E-EK
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
890
38.7
Functional Description
38.7.1 Baud Rate Generator
The baud rate generator provides the bit period clock, also named the baud rate clock, to both the receiver and the
transmitter.
transmitter.
The baud rate generator clock source is selected by setting the USCLKS field in US_MR to one of the following:
The peripheral clock
A division of the peripheral clock, where the divider is product-dependent, but generally set to 8
The external clock, available on the SCK pin
The baud rate generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate
Generator register (US_BRGR). If a zero is written to CD, the baud rate generator does not generate any clock. If
a one is written to CD, the divider is bypassed and becomes inactive.
Generator register (US_BRGR). If a zero is written to CD, the baud rate generator does not generate any clock. If
a one is written to CD, the divider is bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin
must be longer than a peripheral clock period. The frequency of the signal provided on SCK must be at least 3
times lower than the frequency provided on the peripheral clock in USART mode, or 6 times lower in SPI mode.
must be longer than a peripheral clock period. The frequency of the signal provided on SCK must be at least 3
times lower than the frequency provided on the peripheral clock in USART mode, or 6 times lower in SPI mode.
Figure 38-3.
Baud Rate Generator
38.7.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is
field programmed in the US_BRGR. The resulting clock is provided to the receiver as a sampling clock and then
divided by 16 or 8, depending on how the OVER bit in the US_MR is programmed.
field programmed in the US_BRGR. The resulting clock is provided to the receiver as a sampling clock and then
divided by 16 or 8, depending on how the OVER bit in the US_MR is programmed.
If OVER is set, the receiver sampling is eight times higher than the baud rate clock. If OVER is cleared, the
sampling is performed at 16 times the baud rate clock.
sampling is performed at 16 times the baud rate clock.
The baud rate is calculated as per the following formula:
This gives a maximum baud rate of peripheral clock divided by 8, assuming that the peripheral clock is the highest
possible clock and that the OVER bit is set.
possible clock and that the OVER bit is set.
Peripheral clock/DIV
16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
Peripheral clock
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
3
0
1
0
1
FIDI
Baudrate
SelectedClock
8 2
Over
–
(
)CD
(
)
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