Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

The clock for the SDRAMC bus interface (CLK_SDRAMC) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the SDRAMC before disabling the clock, to avoid freezing the SDRAMC in an undefined
state.

The SDRAMC interrupt request line is connected to the interrupt controller. Using the SDRAMC
interrupt requires the interrupt controller to be programmed first.

The initialization sequence is generated by software. The SDRAM devices are initialized by the
following sequence:

1.

SDRAM features must be defined in the CR register by writing the following fields with 
the desired value: asynchronous timings (TXSR, TRAS, TRCD, TRP, TRC, and TWR), 
Number of Columns (NC), Number of Rows (NR), Number of Banks (NB), CAS Latency 
(CAS), and the Data Bus Width (DBW).

2.

For mobile SDRAM devices, Temperature Compensated Self Refresh (TCSR), Drive 
Strength (DS) and Partial Array Self Refresh (PASR) fields must be defined in the Low 
Power Register (LPR).

3.

The Memory Device Type field must be defined in the Memory Device Register 
(MDR.MD).

4.

A No Operation (NOP) command must be issued to the SDRAM devices to start the 
SDRAM clock. The user must write the value one to the Command Mode field in the 
SDRAMC Mode Register (MR.MODE) and perform a write access to any SDRAM 
address.

5.

A minimum pause of 200µs is provided to precede any signal toggle.

6.

An All Banks Precharge command must be issued to the SDRAM devices. The user 
must write the value two to the MR.MODE field and perform a write access to any 
SDRAM address.

7.

Eight Auto Refresh commands are provided. The user must write the value four to the 
MR.MODE field and performs a write access to any SDRAM location eight times.

8.

A Load Mode Register command must be issued to program the parameters of the 
SDRAM devices in its Mode Register, in particular CAS latency, burst type, and burst 
length. The user must write the value three to the MR.MODE field and perform a write 
access to the SDRAM. The write address must be chosen so that BA[1:0] are set to 
zero. See 

 for details about Load Mode Register command.

9.

For mobile SDRAM initialization, an Extended Load Mode Register command must be 
issued to program the SDRAM devices parameters (TCSR, PASR, DS). The user must 
write the value five to the MR.MODE field and perform a write access to the SDRAM. 
The write address must be chosen so that BA[1] or BA[0] are equal to one. See 

 for details about Extended Load Mode Register command.

10. The user must go into Normal Mode, writing the value 0 to the MR.MODE field and per-

forming a write access at any location in the SDRAM.

11. Write the refresh rate into the Refresh Timer Count field in the Refresh Timer Register 

(TR.COUNT). The refresh rate is the delay between two successive refresh cycles. The 
SDRAM device requires a refresh every 15.625µs or 7.81µs. With a 100MHz fre-