Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
224
32072H–AVR32–10/2012
AT32UC3A3
quency, the TR register must be written with the value 1562 (15.625 µs x 100 MHz) or
781 (7.81 µs x 100 MHz).
781 (7.81 µs x 100 MHz).
After initialization, the SDRAM devices are fully functional.
Figure 16-3. SDRAM Device Initialization Sequence
16.7.2
SDRAM Controller Write Cycle
The SDRAMC allows burst access or single access. In both cases, the SDRAMC keeps track of
the active row in each bank, thus maximizing performance. To initiate a burst access, the
SDRAMC uses the transfer type signal provided by the master requesting the access. If the next
access is a sequential write access, writing to the SDRAM device is carried out. If the next
access is a write-sequential access, but the current access is to a boundary page, or if the next
access is in another row, then the SDRAMC generates a precharge command, activates the
new row and initiates a write command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge and active (t
the active row in each bank, thus maximizing performance. To initiate a burst access, the
SDRAMC uses the transfer type signal provided by the master requesting the access. If the next
access is a sequential write access, writing to the SDRAM device is carried out. If the next
access is a write-sequential access, but the current access is to a boundary page, or if the next
access is in another row, then the SDRAMC generates a precharge command, activates the
new row and initiates a write command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge and active (t
RP
) commands and between active
and write (t
RCD
) commands. For definition of these timing parameters, refer to the
.
SDCKE
SDCK
SDRAMC_A[9:0]
A10
SDRAMC_A[12:11]
SDCS
RAS
CAS
SDWE
DQM
Inputs Stable for
200 usec
Valid Command
Precharge All Banks
1st Auto Refresh
8th Auto Refresh
LMR Command
t
MRD
t
RC
t
RP