Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
858
32072H–AVR32–10/2012
AT32UC3A3
• CSTOE: Completion Signal Time-out Error
This bit is set when the completion signal time-out defined by the CSTOR.CSTOCYC field and the CSTOR.CSTOMUL field is
reached.
This bit is cleared when reading the SR register.
• DTOE: Data Time-out Error
This bit is set when the data time-out defined by the DTOR.DTOCYC field and the DTOR.DTOMUL field is reached.
This bit is cleared when reading the SR register.
• DCRCE: Data CRC Error
This bit is set when a CRC16 error is detected in the last data block.
This bit is cleared when reading the SR register.
• RTOE: Response Time-out Error
This bit is set when the response time-out defined by the CMDR.MAXLAT bit is reached.
This bit is cleared when writing the CMDR register.
• RENDE: Response End Bit Error
This bit is set when the end bit of the response is not detected.
This bit is cleared when writing the CMDR register.
• RCRCE: Response CRC Error
This bit is set when a CRC7 error is detected in the response.
This bit is cleared when writing the CMDR register.
• RDIRE: Response Direction Error
This bit is set when the direction bit from card to host in the response is not detected.
This bit is cleared when writing the CMDR register.
• RINDE: Response Index Error
This bit is set when a mismatch is detected between the command index sent and the response index received.
This bit is cleared when writing the CMDR register.
• TXBUFE: TX Buffer Empty Status
This bit is set when the DMA Tx Buffer is empty.
This bit is cleared when the DMA Tx Buffer is not empty.
• RXBUFF: RX BUffer Full Status
This bit is set when the DMA Rx Buffer is full.
This bit is cleared when the DMA Rx Buffer is not full.
• CSRCV: CE-ATA Completion Signal Received
This bit is set when the device issues a command completion signal on the command line.
This bit is cleared when reading the SR register.
• SDIOWAIT: SDIO Read Wait Operation Status
This bit is set when the data bus has entered IO wait state.
This bit is cleared when normal bus operation.
• SDIOIRQB: SDIO Interrupt for Slot B
This bit is cleared when reading the SR register.
This bit is set when a SDIO interrupt on Slot B occurs.
• SDIOIRQA: SDIO Interrupt for Slot A
This bit is set when a SDIO interrupt on Slot A occurs.
This bit is cleared when reading the SR register.
• ENDTX: End of RX Buffer
This bit is set when the DMA Controller transmission is finished.
This bit is cleared when the DMA Controller transmission is not finished.
• ENDRX: End of RX Buffer
This bit is set when the DMA Controller reception is finished.
This bit is cleared when the DMA Controller reception is not finished.
• NOTBUSY: MCI Not Busy
This bit must be used only for write operations.