Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

A block write operation uses a simple busy signalling of the write operation duration on the data (DAT[0]) line: during a data 

transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line 

(DAT[0]) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer 

block length becomes free.

The NOTBUSY bit allows to deal with these different states.

1: MCI is ready for new data transfer.

0: MCI is not ready for new data transfer.

This bit is cleared at the end of the card response.

This bit is set when the busy state on the data line is ended. This corresponds to a free internal data receive buffer of the card.

Refer to the MMC or SD Specification for more details concerning the busy behavior.

This bit is set when the current data transfer is in progress.

This bit is cleared at the end of the CRC16 calculation

1: The current data transfer is still in progress.

0: No data transfer in progress.

This bit must be used only for Write Operations.

This bit is set when a data block transfer has ended.

This bit is cleared when reading SR.

1: a data block transfer has ended, including the CRC16 Status transmission, the bit is set for each transmitted CRC Status.

0: A data block transfer is not yet finished.

Refer to the MMC or SD Specification for more details concerning the CRC Status.

This bit is set when the last data written in the TDR register has been transferred.

This bit is cleared the last data written in the TDR register has not yet been transferred.

This bit is set when the data has been received since the last read of the RDR register.

This bit is cleared when the data has not yet been received since the last read of the RDR register.

This bit is set when the last command has been sent.

This bit is cleared when writing the CMDR register