Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
20
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
7.3
Power-Up
This section summarizes the power-up sequence of the SAM D21. The behavior after power-up is controlled by the
Power Manager. Refer to
Power Manager. Refer to
for details.
7.3.1
Starting of Clocks
After power-up, the device is set to its initial state and kept in reset, until the power has stabilized throughout the device.
Once the power has stabilized, the device will use a 1MHz clock. This clock is derived from the 8MHz Internal Oscillator
(OSC8M), which is divided by eight and used as a clock source for generic clock generator 0. Generic clock generator 0
is the main clock for the Power Manager (PM).
Once the power has stabilized, the device will use a 1MHz clock. This clock is derived from the 8MHz Internal Oscillator
(OSC8M), which is divided by eight and used as a clock source for generic clock generator 0. Generic clock generator 0
is the main clock for the Power Manager (PM).
Some synchronous system clocks are active, allowing software execution.
Refer to the “Clock Mask Register” section in
for the list of default peripheral clocks
running. Synchronous system clocks that are running are by default not divided and receive a 1MHz clock through
generic clock generator 0. Other generic clocks are disabled except GCLK_WDT, which is used by the Watchdog Timer
(WDT).
generic clock generator 0. Other generic clocks are disabled except GCLK_WDT, which is used by the Watchdog Timer
(WDT).
7.3.2
I/O Pins
After power-up, the I/O pins are tri-stated.
7.3.3
Fetching of Initial Instructions
After reset has been released, the CPU starts fetching PC and SP values from the reset address, which is 0x00000000.
This address points to the first executable address in the internal flash. The code read from the internal flash is free to
configure the clock system and clock sources. Refer to
This address points to the first executable address in the internal flash. The code read from the internal flash is free to
configure the clock system and clock sources. Refer to
for details. Refer to the ARM Architecture
Reference Manual for more information on CPU startup (
http://www.arm.com
).
7.4
Power-On Reset and Brown-Out Detector
The SAM D21 embeds three features to monitor, warn and/or reset the device:
z
POR: Power-on reset on VDDANA
z
BOD33: Brown-out detector on VDDANA
z
BOD12: Voltage Regulator Internal Brown-out detector on VDDCORE. The Voltage Regulator Internal BOD is
calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration should
not be changed if the user row is written to assure the correct behavior of the BOD12.
calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration should
not be changed if the user row is written to assure the correct behavior of the BOD12.
7.4.1
Power-On Reset on VDDANA
POR monitors VDDANA. It is always activated and monitors voltage at startup and also during all the sleep modes. If
VDDANA goes below the threshold voltage, the entire chip is reset.
VDDANA goes below the threshold voltage, the entire chip is reset.
7.4.2
Brown-Out Detector on VDDANA
BOD33 monitors VDDANA. Refer to
7.4.3
Brown-Out Detector on VDDCORE
Once the device has started up, BOD12 monitors the internal VDDCORE.