Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

Product codes
ATSAMD21-XPRO
Page of 1018
318
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
19.8.2 DMAC SRAM Registers
19.8.2.1  Block Transfer Control
The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name:
BTCTRL
Offset:
0x00
z
Bits 15:13 – STEPSIZE[2:0]: Address Increment Step Size
These bits select the address increment step size, as shown in 
nation address, depending on STEPSEL setting.
Table 19-11. Address Increment Step Size
z
Bit 12 – STEPSEL: Step Selection
This bit selects if source or destination addresses are using the step size settings, according to 
.
Table 19-12. Step Selection
z
Bit 11 – DSTINC: Destination Address Increment Enable
0: The Destination Address Increment is disabled.
1: The Destination Address Increment is enabled.
Writing a zero to this bit will disable the destination address incrementation. The address will be kept fixed during 
the data transfer.
Bit
15
14
13
12
11
10
9
8
STEPSIZE[2:0]
STEPSEL
DSTINC
SRCINC
BEATSIZE[1:0]
Bit
7
6
5
4
3
2
1
0
BLOCKACT[1:0]
EVOSEL[1:0]
VALID
STEPSIZE[2:0]
Name
Description
0x0
X1
Next ADDR <- ADDR + BEATSIZE * 1
0x1
X2
Next ADDR <- ADDR + BEATSIZE * 2
0x2
X4
Next ADDR <- ADDR + BEATSIZE * 4
0x3
X8
Next ADDR <- ADDR + BEATSIZE * 8
0x4
X16
Next ADDR <- ADDR + BEATSIZE * 16
0x5
X32
Next ADDR <- ADDR + BEATSIZE * 32
0x6
X64
Next ADDR <- ADDR + BEATSIZE * 64
0x7
X128
Next ADDR <- ADDR + BEATSIZE * 128
STEPSEL
Name
Description
0x0
DST
Step size settings apply to the destination address
0x1
SRC
Step size settings apply to the source address