Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
319
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
Writing a one to this bit will enable the destination address incrementation. By default, the destination address is
incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register,
as shown in
incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register,
as shown in
z
Bit 10 – SRCINC: Source Address Increment Enable
0: The Source Address Increment is disabled.
1: The Source Address Increment is enabled.
Writing a zero to this bit will disable the source address incrementation. The address will be kept fixed during the
data transfer.
Writing a one to this bit will enable the source address incrementation. By default, the source address is incre-
mented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register, as
shown in
0: The Source Address Increment is disabled.
1: The Source Address Increment is enabled.
Writing a zero to this bit will disable the source address incrementation. The address will be kept fixed during the
data transfer.
Writing a one to this bit will enable the source address incrementation. By default, the source address is incre-
mented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register, as
shown in
.
z
Bits 9:8 – BEATSIZE[1:0]: Beat Size
These bits define the size of one beat, as shown in
These bits define the size of one beat, as shown in
. A beat is the size of one data transfer bus access,
and the setting apply to both read and write accesses.
Table 19-13. Beat Size
z
Bits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 4:3 – BLOCKACT[1:0]: Block Action
These bits define what actions the DMAC should take after a block transfer has completed. The available actions
are listed in
These bits define what actions the DMAC should take after a block transfer has completed. The available actions
are listed in
.
Table 19-14. Block Action
z
Bits 2:1 – EVOSEL[1:0]: Event Output Selection
These bits define the event output selection, as shown in
These bits define the event output selection, as shown in
BEATSIZE[1:0]
Name
Description
0x0
BYTE
8-bit access
0x1
HWORD
16-bit access
0x2
WORD
32-bit access
0x3
Reserved
BLOCKACT[1:0]
Name
Description
0x0
NOACT
No action
0x1
INT
Channel in normal operation and block interrupt
0x2
SUSPEND
Channel suspend operation is completed
0x3
BOTH
Both channel suspend operation and block interrupt