Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

If the operation is a read, the 10-bit address will be followed by a repeated START and reception of “11110 ADDR[9:8] 1” 
and the second address interrupt will be received with the DIR bit set. The slave matches on the second address as it 
remembers that is was addressed by the previous 10-bit address.

When the group command bit is set (CTRLB.GCMD) and 7-bit addressing is used, a STOP interrupt will be generated if 
the slave has been addressed since the last STOP condition.

The group command protocol is used to send commands to more than one device. The commands are sent in one 
continuous transmission with a single STOP condition at the end. When the STOP condition is detected by the slaves 
addressed during the group command, they all begin executing the command they received. 

 shows an example where this slave is addressed by ADDRESS 1. This slave is addressed after a repeated 

START condition. There can be multiple slaves addressed before and after, then at the end of the group command, a 
single STOP is generated by the master. At this point a STOP interrupt is asserted.

The I

2

C hardware incorporates three hardware SCL low time-outs which allows a time-out to occur for SMBus SCL low 

time-out, master extend time-out, and slave extend time-out. These time-outs are driven by the GCLK_SERCOM_SLOW 
clock. The GCLK_SERCOM_SLOW clock is used to accurately time the time-out and must be configured to used a 
32kHz oscillator. The I

2

C interface also allows for an SMBus compatible SDA hold time.

z

T

TIMEOUT

: SCL low time of 25-35 ms. – Measured for a single SCL low period. Enabled by bit 

CTRLA.LOWTOUTEN.