Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

z

T

LOW:SEXT

:Cumulative clock low extend time of 25 ms – Measured as the cumulative SCL low extend time by a 

slave device in a single message from the initial START to the STOP. Enabled by bit CTRLA.SEXTTOEN.

z

T

LOW:MEXT

: Cumulative clock low extend time of 10 ms. – Measured as the cumulative SCL low extend time by 

the master device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. Enabled by bit 
(CTRLA.MEXTTOEN.

The I

2

C interface incorporates a special smart mode that simplifies application code and minimizes the user interaction 

needed to keep hold of the I

2

C protocol. The smart mode accomplishes this by letting the reading of DATA.DATA 

automatically issue an ACK or NACK based on the state of CTRLB.ACKACT.

Setting the Pin Usage bit in the Control A register (CTRLA.PINOUT) for master or slave to 4-wire mode enables 
operation as shown in 

. In this mode, the internal I

2

C tri-state drivers are bypassed, and an external, I

2

C-

compliant tri-state driver is needed when connecting to an I

2

C bus.

Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick 
command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address. At 
this point, the software can either issue a stop command or a repeated start by writing CTRLB.CMD or ADDR.ADDR.

SCL/SDA

 

pad

I2C

 

Driver

SCL_OUT/

 

SDA_OUT

 

pad

PINOUT

PINOUT

SCL_IN/
SDA_IN

SCL_OUT/
SDA_OUT