Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
682
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
z
Bit 2 – ONESHOT: One-Shot
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the
next overflow/underflow condition or a stop command.
0: The TCC will count continuously.
1: The TCC will stop counting on the next underflow/overflow condition.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the one-shot operation.
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the
next overflow/underflow condition or a stop command.
0: The TCC will count continuously.
1: The TCC will stop counting on the next underflow/overflow condition.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the one-shot operation.
z
Bit 1 – LUPD: Lock Update
This bit controls the update operation of the TCC buffered registers. When this bit is set, no update of the buffered
registers is performed, even though an UPDATE condition has occurred. Locking the update can be used to
ensure that all buffer registers are loaded with the desired values, before an update is performed. After all the buf-
fer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
1: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are not copied into CCx, PER, PGV, PGE
and SWAPx registers.
0: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are copied into CCx, PER, PGV, PGE
and SWAPx registers on timer Overflow/underflow or retrigger condition.
This bit controls the update operation of the TCC buffered registers. When this bit is set, no update of the buffered
registers is performed, even though an UPDATE condition has occurred. Locking the update can be used to
ensure that all buffer registers are loaded with the desired values, before an update is performed. After all the buf-
fer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
1: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are not copied into CCx, PER, PGV, PGE
and SWAPx registers.
0: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are copied into CCx, PER, PGV, PGE
and SWAPx registers on timer Overflow/underflow or retrigger condition.
z
Bit 0 – DIR: Counter Direction
This bit is used to change the direction of the counter.
0: The timer/counter is counting up (incrementing).
1: The timer/counter is counting down (decrementing).
Writing a zero to this bit has no effect
Writing a one to this bit will make the counter count down.
This bit is used to change the direction of the counter.
0: The timer/counter is counting up (incrementing).
1: The timer/counter is counting down (decrementing).
Writing a zero to this bit has no effect
Writing a one to this bit will make the counter count down.
0x1
SET
Set index: cycle B will be forced in the next cycle
0x2
CLEAR
Clear index: cycle A will be forced in the next cycle
0x3
HOLD
Hold index: the next cycle will be the same as the current
cycle
cycle
IDXCMD[1:0]
Name
Description