Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
683
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
30.8.4 Synchronization Busy
Name:
SYNCBUSY
Offset:
0x08
Reset:
0x00000000
Property:
-
z
Bits 31:23 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 22:19 – CCBx [x=3..0]: Compare Channel Buffer x Busy
This bit is cleared when the synchronization of Compare/Capture Channel x Buffer register between the clock
domains is complete.
This bit is set when the synchronization of Compare/Capture Channel x Buffer register between clock domains is
started.
CCBx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to
each TCC feature list.
This bit is set when the synchronization of CCBx register between clock domains is started.
This bit is cleared when the synchronization of Compare/Capture Channel x Buffer register between the clock
domains is complete.
This bit is set when the synchronization of Compare/Capture Channel x Buffer register between clock domains is
started.
CCBx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to
each TCC feature list.
This bit is set when the synchronization of CCBx register between clock domains is started.
z
Bit 18 – PERB: Period Buffer Busy
This bit is cleared when the synchronization of PERB register between the clock domains is complete.
This bit is set when the synchronization of PERB register between clock domains is started.
This bit is cleared when the synchronization of PERB register between the clock domains is complete.
This bit is set when the synchronization of PERB register between clock domains is started.
z
Bit 17 – WAVEB: Wave Buffer Busy
This bit is cleared when the synchronization of WAVEB register between the clock domains is complete.
This bit is cleared when the synchronization of WAVEB register between the clock domains is complete.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
CCB3
CCB2
CCB1
CCB0
PERB
WAVEB
PATTB
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
CC3
CC2
CC1
CC0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PER
WAVE
PATT
COUNT
STATUS
CTRLB
ENABLE
SWRST
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0