Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
773
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
1: The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream
Resume interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding inter-
rupt request.
Resume interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding inter-
rupt request.
z
Bit 5 – EORSM: End Of Resume Interrupt Enable
0: The End Of Resume interrupt is disabled.
1: The End Of Resume interrupt is enabled and an interrupt request will be generated when the End Of Resume
interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End Of Resume interrupt Enable bit and disable the corresponding interrupt
request.
0: The End Of Resume interrupt is disabled.
1: The End Of Resume interrupt is enabled and an interrupt request will be generated when the End Of Resume
interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End Of Resume interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 4 – WAKEUP: Wake-Up Interrupt Enable
0: The Wake Up interrupt is disabled.
1: The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
0: The Wake Up interrupt is disabled.
1: The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
z
Bit 3 – EORST: End of Reset Interrupt Enable
0: The End of Reset interrupt is disabled.
1: The End of Reset interrupt is enabled and an interrupt request will be generated when the End of Reset interrupt
Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End of Reset interrupt Enable bit and disable the corresponding interrupt
request.
0: The End of Reset interrupt is disabled.
1: The End of Reset interrupt is enabled and an interrupt request will be generated when the End of Reset interrupt
Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End of Reset interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 2 – SOF: Start-of-Frame Interrupt Enable
0: The Start-of-Frame interrupt is disabled.
1: The Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Start-of-Frame
interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
0: The Start-of-Frame interrupt is disabled.
1: The Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Start-of-Frame
interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 0– SUSPEND: Suspend Interrupt Enable
0: The Suspend interrupt is disabled.
1: The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend interrupt Flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt request.
0: The Suspend interrupt is disabled.
1: The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend interrupt Flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt request.