Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
803
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
31.8.5.6 Host Interrupt Enable Register Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set (INTENSET) register.
will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name:
INTENCLR
Offset:
0x14
Reset:
0x0000
Property:
Write-Protected
z
Bits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 9 – DDISC: Device Disconnection Interrupt Enable
0: The Device Disconnection interrupt is disabled.
1: The Device Disconnection interrupt is enabled and an interrupt request will be generated when the Device Dis-
connection interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Disconnection interrupt Enable bit and disable the corresponding inter-
rupt request.
0: The Device Disconnection interrupt is disabled.
1: The Device Disconnection interrupt is enabled and an interrupt request will be generated when the Device Dis-
connection interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Disconnection interrupt Enable bit and disable the corresponding inter-
rupt request.
z
Bit 8 – DCONN: Device Connection Interrupt Enable
0: The Device Connection interrupt is disabled.
1: The Device Connection interrupt is enabled and an interrupt request will be generated when the Device Con-
nection interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Connection interrupt Enable bit and disable the corresponding inter-
rupt request.
0: The Device Connection interrupt is disabled.
1: The Device Connection interrupt is enabled and an interrupt request will be generated when the Device Con-
nection interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Connection interrupt Enable bit and disable the corresponding inter-
rupt request.
z
Bit 7 – RAMACER: RAM Access Interrupt Enable
0: The RAM Access interrupt is disabled.
1: The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access interrupt
Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt
request.
0: The RAM Access interrupt is disabled.
1: The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access interrupt
Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 6 – UPRSM: Upstream Resume from Device Interrupt Enable
0: The Upstream Resume interrupt is disabled.
0: The Upstream Resume interrupt is disabled.
Bit
15
14
13
12
11
10
9
8
DDISC
DCONN
Access
R/
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RAMACER
UPRSM
DNRSM
WAKEUP
RST
HSOF
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Reset
0
0
0
0
0
0
0
0