Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
804
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
1: The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream
Resume interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding inter-
rupt request.
Resume interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding inter-
rupt request.
z
Bit 5 – DNRSM: Down Resume Interrupt Enable
0: The Down Resume interrupt is disabled.
1: The Down Resume interrupt is enabled and an interrupt request will be generated when the Down Resume
interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Down Resume interrupt Enable bit and disable the corresponding interrupt
request.
0: The Down Resume interrupt is disabled.
1: The Down Resume interrupt is enabled and an interrupt request will be generated when the Down Resume
interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Down Resume interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 4 – WAKEUP: Wake Up Interrupt Enable
0: The Wake Up interrupt is disabled.
1: The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
0: The Wake Up interrupt is disabled.
1: The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
z
Bit 3 – RST: BUS Reset Interrupt Enable
0: The Bus Reset interrupt is disabled.
1: The Bus Reset interrupt is enabled and an interrupt request will be generated when the Bus Reset interrupt Flag
is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Bus Reset interrupt Enable bit and disable the corresponding interrupt
request.
0: The Bus Reset interrupt is disabled.
1: The Bus Reset interrupt is enabled and an interrupt request will be generated when the Bus Reset interrupt Flag
is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Bus Reset interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 2 – HSOF: Host Start-of-Frame Interrupt Enable
0: The Host Start-of-Frame interrupt is disabled.
1: The Host Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Host Start-of-
Frame interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Host Start-of-Frame interrupt Enable bit and disable the corresponding inter-
rupt request.
0: The Host Start-of-Frame interrupt is disabled.
1: The Host Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Host Start-of-
Frame interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Host Start-of-Frame interrupt Enable bit and disable the corresponding inter-
rupt request.
z
Bits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.