Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
821
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
31.8.6.8 Host Interrupt Pipe Set Register
Name:
PINTENSET
Offset:
0x109 + (n x 0x20)
Reset:
0x0000
Property:
Write-Protected
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.
This register is cleared by USB reset or when PEN[n] is zero.
register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.
This register is cleared by USB reset or when PEN[n] is zero.
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 5 – STALL: Stall Interrupt Enable
0: The Stall interrupt is disabled.
1: The Stall interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Stall interrupt.
0: The Stall interrupt is disabled.
1: The Stall interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Stall interrupt.
z
Bit 4 – TXSTP: Transmitted Setup Interrupt Enable
0: The Transmitted Setup interrupt is disabled.
1: The Transmitted Setup interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmitted Setup interrupt.
0: The Transmitted Setup interrupt is disabled.
1: The Transmitted Setup interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmitted Setup interrupt.
z
Bit 3 – PERR: Pipe Error Interrupt Enable
0: The Pipe Error interrupt is disabled.
1: The Pipe Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Pipe Error interrupt.
0: The Pipe Error interrupt is disabled.
1: The Pipe Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Pipe Error interrupt.
z
Bit 2 – TRFAIL: Transfer Fail Interrupt Enable
0: The Transfer Fail interrupt is disabled.
1: The Transfer Fail interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
0: The Transfer Fail interrupt is disabled.
1: The Transfer Fail interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
z
Bit 1 – TRCPT1: Transfer Complete 1 interrupt Enable
0: The Transfer Complete 1 interrupt is disabled.
1: The Transfer Complete 1 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete interrupt Enable bit 1.
0: The Transfer Complete 1 interrupt is disabled.
1: The Transfer Complete 1 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete interrupt Enable bit 1.
Bit
7
6
5
4
3
2
1
0
STALL
TXSTP
PERR
TRFAIL
TRCPT1
TRCPT0
Access
R
R
RW1
RW1
RW1
RW1
RW1
RW1
Reset
0
0
0
0
0
0
0
0