Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet

106

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

Note:

1.

A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is 
ignored, but the set or clear is done at TOP. See 

 for more details.

These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the 
OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data 
Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver.

When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting. 

 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode 

(non-PWM).

 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode.

Note:

1.

A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is 
ignored, but the set or clear is done at TOP. See 

 for more details.

 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. 

0

0

Normal port operation, OC0A disconnected.

0

1

WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.

1

0

Clear OC0A on Compare Match when up-counting. Set OC0A on 
Compare Match when down-counting.

1

1

Set OC0A on Compare Match when up-counting. Clear OC0A on 
Compare Match when down-counting.

0

0

Normal port operation, OC0B disconnected.

0

1

Toggle OC0B on Compare Match

1

0

Clear OC0B on Compare Match

1

1

Set OC0B on Compare Match

0

0

Normal port operation, OC0B disconnected.

0

1

Reserved

1

0

Clear OC0B on Compare Match, set OC0B at BOTTOM,
(non-inverting mode)

1

1

Set OC0B on Compare Match, clear OC0B at BOTTOM,
(inverting mode).