Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
236
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
23.3
Register Description
23.3.1 ADCSRB – ADC Control and Status Register B
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer
selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the
negative input of the Analog Comparator. For a detailed description of this bit, see
selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the
negative input of the Analog Comparator. For a detailed description of this bit, see
.
23.3.2 ACSR – Analog Comparator Control and Status Register
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any
time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When
changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise an interrupt can occur when the bit is changed.
time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When
changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise an interrupt can occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator.
When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. When the bandgap
reference is used as input to the Analog Comparator, it will take a certain time for the voltage to stabilize. If not
stabilized, the first conversion may give a wrong value. See
When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. When the bandgap
reference is used as input to the Analog Comparator, it will take a certain time for the voltage to stabilize. If not
stabilized, the first conversion may give a wrong value. See
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization
introduces a delay of 1 - 2 clock cycles.
introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and
ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set.
ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is
cleared by writing a logic one to the flag.
ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set.
ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is
cleared by writing a logic one to the flag.
1
0
100
ADC4
1
0
101
ADC5
1
0
110
ADC6
1
0
111
ADC7
Table 23-1.
Analog Comparator Multiplexed Input (Continued)
ACME
ADEN
MUX2...0
Analog Comparator Negative Input
Bit
7
6
5
4
3
2
1
0
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
ADCSRB
Read/Write
R
R/W
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
ACSR
Read/Write
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
N/A
0
0
0
0
0